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32nd International conference on Flexible Automation and Intelligent Manufacturing, FAIM 2023

32nd International Conference on Flexible Automation and Int...

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32nd International conference on Flexible Automation and Intelligent Manufacturing, FAIM 2023

ISBN: (纸本)9783031381645

The proceedings contain 239 papers. The special focus in this conference is on . The topics include: A Review of Value Stream Mapping (VSM) for Viable Business Process Management Among Agro-Allied Companies During the 4IR;outsourcing Optimization in Footwear Industry: The Case of a Portuguese Company;UWB-Based Indoor Navigation in a Flexible Manufacturing System Using a Custom Quadrotor UAV;real-Time Defect and Object Detection in Assembly Line: A Case for In-Line Quality Inspection;Using Computer Vision to Improve SME Performance;Cyber-Physical Systems Based Smart Manufacturing of Disinfectants: A Need, and Solution Driven by COVID-19 Pandemic;CPPS-3D: A Methodology to Support Cyber Physical Production Systems Design, Development and Deployment;reinforcement Learning-Based Model for Optimization of Cloud Manufacturing-Based Multi Objective Resource Scheduling: A Review;an Overview of Explainable Artificial Intelligence in the Industry 4.0 Context;Analyzing the Effects of Different 3D-Model Acquisition Methods for Synthetic AI Training Data Generation and the Domain Gap;improving Regulations for Automated Design Checking Through Decision Analysis Good Practices: A Conceptual Application to the Construction Sector;environment for the Design and Automation of New Cable-Driven parallel Robot architectures;preliminary Design of an Automatic Palletizing System During the Pre-sales Stage;a New Equipment for Automatic Calibration of the Semmes-Weinstein Monofilament;measuring the Moment-Curvature Relationship of a Steerable Catheter Using a Load Cell and Stereovision System;study of the Best Operational Parameters in Laser Marking of Plastic Parts;Laser Marking on White-Coloured Polyoxymethylene (POM) Polymer Substrate: Challenges and Perspectives;influence of Laser Beam Intensity Distribution on Keyhole Geometry and Process Stability Using Green Laser Radiation;advanced Characterization techniques of Multi-material Machining Tool Coatings.

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HPC master design: experience from Pisa 33

HPC master design: experience from Pisa

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33rd Euromicro International conference on parallel, Distributed, and Network-Based Processing, PDP 2025

作者： Danelutto, Marco Univ. of Pisa Dept. of Computer Science Italy

ISBN: (纸本)9798331524937

HPC is a widely used term, often referred to the applications, architectures and programming models and tools targeting highly parallel machines such as those of the *** lists. Recent advances in computing hardware resources require application of HPC techniques when using much smaller machines. Indeed, proper parallel programming tools and applications are needed also to exploit parallel hardware resources in personal computers (laptops, desktops, servers). This paper outlines key challenges in designing master's degree programs in HPC and shares lessons learned from various experiences in developing and implementing such programs in Italy and Europe. © 2025 IEEE.

关键词： parallel programming

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Compiler-Driven performance workshop

Compiler-Driven performance workshop

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conference of the Centre for Advanced Studies on Collaborative Research - 29th Annual International conference on Computer Science and Software Engineering, CASCON 2019

作者： Verbrugge, Clark Copeland, Reid Nelson Amaral, J. Tsang, Whitney T. McGill University Montréal QC Canada IBM Toronto Laboratory MarkhamON Canada University of Alberta EdmontonAB Canada

The compiler-driven performance workshop consisted of the presentation of reports on research progress at various academic and industrial sites across Canada and in the United States. Topics discussed in the workshop included, among others: • innovative compiler analysis, transformation, and optimization techniques • languages, compilers, and optimization techniques for multicore processors and other parallel architectures • analysis and compilation techniques for dynamic programming languages • compiling for streaming or heterogeneous hardware • dynamic compilation for high-performance and real-time environments • compilation and optimization for scripting languages • compilation techniques for reducing power • program safety • whole system optimization and analysis • tools and infrastructure for compiler research. © 2019 Copyright held by the owner/author(s).

关键词： parallel architectures

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Initial Results on the Effectiveness of Distributed Edge Detection for Large Image Data Sets

Initial Results on the Effectiveness of Distributed Edge Det...

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SoutheastCon conference

作者： Renato, Ivanescu Constantin Mihai, Mocanu Univ Craiova Dept Comp & Informat Technol Craiova Romania

ISBN: (纸本)9781665406529

Image data is expanding rapidly, along with technology development, so efficient solutions must be considered to achieve high, real-time performance in the case of processing large image datasets. parallel processing is increasingly used as an attractive alternative to improve the performance, when using existing distributed architectures but also for sequential commodity computers. It can provide speedup, efficiency, reliability, incremental growth, and flexibility. We present such an alternative and stress the effectiveness of the methods to accelerate computations on a small cluster of PCs compared to a single CPU. Our paper is focused on applying edge detection on large image data sets, as a fundamental and challenging task in image processing and computer vision. Five different techniques, mainly Sobel, Prewitt, LoG, Canny, and Roberts, are compared in a simple experimental setup that includes the OpenCV library functions for image pixels manipulation. Gaussian blur is used to reduce high-frequency components to manage the noise that edge detection is impacted by. Overall, this work is part of a more extensive investigation of image segmentation methods on large image datasets, but the results presented are relevant and show the effectiveness of our approach.

关键词： parallel image processing edge detection OpenCV MPI

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parallel architectures and compilation techniques - conference proceedings, PACT

Parallel Architectures and Compilation Techniques - Conferen...

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6th Workshop on Data-Flow Execution Models for Extreme Scale Computing, DFM 2016

The proceedings contain 4 papers. The topics discussed include: data-driven execution of the tile LU decomposition;tree-based read-only data-chunks for NVRAM programming;CnC: a dependence programming mode;and challeng...

ISBN: (纸本)9781450361996

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VLSI architectures of Three Operand Binary Adders 1

VLSI Architectures of Three Operand Binary Adders

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1st IEEE International conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems, ICAECIS 2023

作者： Shravan, Chintham Marri, Sai Krishna Kampasati, Triveni Rgukt Dept. of Ece Basar India

ISBN: (纸本)9798350348057

Directly or indirectly adders are the basic elements in almost all digital circuits, three operand adders are the basic building blocks in LCG(Linear congruential generator) based pseudo-random bit generators. Elementary adders are fast, area and power efficient for small bit sizes. Carry save adder computes the addition in O(n) time complexity, due to its ripple carry stage. parallel prefix adders such as han carlson compute the addition in O(log(n)) time complexity but at the cost of additional circuitry. Hence new high-speed power-efficient adder architecture is proposed which uses four stages to compute the addition, which consumes less power, and the adder delay decreases to O(n/2). Even though it is not much faster than the High speed Area efficient vlsi architecture of three operand adder(HSAT3), it computes the addition by utilizing less power. The proposed architecture is implemented using Verilog HDL in Xilinx 14.7 design environment and it is evident that this adder architecture is 2 times faster than the carry save adder and 1, 1.5, 1.75 times faster than the hybrid adder structure for 32, 64, 128 bits respectively. Also, power utilization is 1.95 times lesser than HSAT3, 1.94 times lesser than the han carlson adder, and achieves the lowest PDP than the existing three operand techniques. © 2023 IEEE.

关键词： Adders

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Scope states: Guarding safety of name resolution in parallel type checkers 35

Scope states: Guarding safety of name resolution in parallel...

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35th European conference on Object-Oriented Programming, ECOOP 2021

作者： Van Antwerpen, Hendrik Visser, Eelco Delft University of Technology Netherlands

ISBN: (纸本)9783959771900

Compilers that can type check compilation units in parallel can make more efficient use of multi-core architectures, which are nowadays widespread. Developing parallel type checker implementations is complicated by the need to handle concurrency and synchronization of parallel compilation units. Dependencies between compilation units are induced by name resolution, and a parallel type checker needs to ensure that units have defined all relevant names before other units do a lookup. Mutually recursive references and implicitly discovered dependencies between compilation units preclude determining a static compilation order for many programming languages. In this paper, we present a new framework for implementing hierarchical type checkers that provides implicit parallel execution in the presence of dynamic and mutual dependencies between compilation units. The resulting type checkers can be written without explicit handling of communication or synchronization between different compilation units. We achieve this by providing type checkers with an API for name resolution based on scope graphs, a language-independent formalism that supports a wide range of binding patterns. We introduce the notion of scope state to ensure safe name resolution. Scope state tracks the completeness of a scope, and is used to decide whether a scope graph query between compilation units must be delayed. Our framework is implemented in Java using the actor paradigm. We evaluated our approach by parallelizing the solver for Statix, a meta-language for type checkers based on scope graphs, using our framework. This parallelizes every Statix-based type checker, provided its specification follows a split declaration-type style. Benchmarks show that the approach results in speedups for the parallel Statix solver of up to 5.0x on 8 cores for real-world code bases. © 2021 Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing. All rights reserved.

关键词： Computer architecture

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Efficient Task-Mapping of parallel Applications Using a Space-Filling Curve 22

Efficient Task-Mapping of Parallel Applications Using a Spac...

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proceedings of the International conference on parallel architectures and compilation techniques

作者： Oh-Kyoung Kwon Ji-hoon Kang Seungchul Lee Wonjung Kim Junehwa Song Korea Advanced Institute of Science and Technology Daejeon Republic of Korea Korea Institute of Science and Technology Information Daejeon Republic of Korea

ISBN: (纸本)9781450398688

Improving the communication performance of parallel programs is an important but difficult problem in a large-scale distributed memory-based cluster. Efforts to improve parallel scalability often face severe huddles in managing communication overheads. This paper proposes a framework of a space-filing curve(SFC)-based task-remapping for communication intensive parallel applications. An SFC-based mapping, when applied for task-mapping of parallel applications preserves locality in terms of communications and produce a less fragmented task-mapping, reducing communication overheads. The framework also provides tools for performance analysis to see if the proposed task-mapping is appropriate for a given application running on a target system. It further develops a binary classifier as a predictor to decide whether or not to apply the proposed mapping before run-time. We evaluate the framework with three communication intensive applications in Cartesian coordinates: P3DFFT solver and Channel code using 2D domain decomposition model, and Poisson solver using 3D domain decomposition. The evaluation is conducted on a large-scale cluster system of fat-tree topology with up to 1,024 compute nodes. The proposed task-mapping achieves the overall performance improvement ranging from ~30% to ~66% over the baseline approach depending on the workloads. Also, when used in combination with the binary classifier-based predictor, it achieves the expected performance gains from 4% to 8%.

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23rd International conference on Computational Science, ICCS 2023

23rd International Conference on Computational Science, ICCS...

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23rd International conference on Computational Science, ICCS 2023

ISBN: (纸本)9783031360237

The proceedings contain 282 papers. The special focus in this conference is on Computational Science. The topics include: Improving the Performance of Task-Based Linear Algebra Software with Autotuning techniques on Heterogeneous architectures;SLAM Methods for Augmented Reality Systems for Flight Simulators;ensemble Based Learning for Automated Safety Labeling of Prescribed Fires;Memory-Efficient All-Pair Suffix-Prefix Overlaps on GPU;Linking Scholarly Datasets—The EOSC Perspective;from Online Behaviours to Images: A Novel Approach to Social Bot Detection;Combining Outlierness Scores and Feature Extraction techniques for Improvement of OoD and Adversarial Attacks Detection in DNNs;turning Flight Simulation with Fluid-Rigid Body Interaction for Flying Car with Contra-Rotating Propellers;An Intelligent Transportation System for Tsunamis Combining CEP, CPN and Fuzzy Logic;A Contrastive Self-distillation BERT with Kernel Alignment-Based Inference;multi-agent Cellular Automaton Model for Traffic Flow Considering the Heterogeneity of Human Delay and Accelerations;FAIR-FATE: Fair Federated Learning with Momentum;excessive Internet Use in the Organizational Context: A Proposition of the New Instrument to Measure Cyberloafing at Work;data Integration Landscapes: The Case for Non-optimal Solutions in Network Diffusion Models;automatic Delta-Adjustment Method Applied to Missing Not At Random Imputation;enhanced Emotion and Sentiment Recognition for Empathetic Dialogue System Using Big Data and Deep Learning Methods;Forecasting Cryptocurrency Prices Using Contextual ES-adRNN with Exogenous Variables;towards Automatic Generation of Digital Twins: Graph-Based Integration of Smart City Datasets;a Moral Foundations Dictionary for the European Portuguese Language: The Case of Portuguese Parliamentary Debates;siamese Autoencoder-Based Approach for Missing Data Imputation;parallel Adjoint Taping Using MPI;graph-Level Representations Using Ensemble-Based Readout Functions;B2 -FedGAN: B

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23rd International conference on Computational Science, ICCS 2023

23rd International Conference on Computational Science, ICCS...

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23rd International conference on Computational Science, ICCS 2023

ISBN: (纸本)9783031360206

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