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Virtual International conference on Futuristic Communication and Network Technologies, VICFCNT 2021

Virtual International Conference on Futuristic Communication...

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Virtual International conference on Futuristic Communication and Network Technologies, VICFCNT 2021

ISBN: (纸本)9789811997471

The proceedings contain 50 papers. The special focus in this conference is on Virtual Futuristic Communication and Network Technologies. The topics include: Levy Flight-Based Black Widow Optimization for Power Network Reconfiguration;Exploratory Spatial Data Analysis (ESDA) Based on Geolocational Area;modified Hill Cipher with Invertible Key Matrix Using Radix 64 Conversion;BT Classification Using Deep Learning techniques from MRI Images—A Review;design and Development of Automated Smart Warehouse Solution;emotion Recognition from Facial Expressions Using Videos and Prototypical Network for Human–Computer Interaction;a Review on Early Diagnosis of Parkinson’s Disease Using Speech Signal Parameters Based on Machine Learning Technique;Investigation of Attention Deficit Hyperactivity Disorder with Image Enhancement and Calculation of Brain Grey Matter Volume using Anatomical and Resting-State functional MRI;implementation of e-Healthcare Data Acquisition System Using IoT (Internet of Things);VLSI Implementation for Noise Suppression Using parallel Median Filtering Technique;Investigation on Performance of CNN architectures for Land Use Classification;Enhanced ATM Security Using Facial Recognition, Fingerprint Authentication, and WEB Application;Spatial and Temporal Analysis of Water Bodies in Bengaluru Urban Using GIS and Satellite Image Processing;shoreline Change Detection and Coastal Erosion Monitoring: A Case Study in Kappil–Pesolikal Beach Region of the Malabar Coast, Kerala;a Novel Approach with Hybrid Technique for Monitoring and Leakage Detection of Water Pipeline Using IoT;VGG-16 Architecture for MRI Brain Tumor Image Classification;cryo-facies Mapping of Karakoram and Himalayan Glaciers Using Multispectral Data;ethereum-Based Certificate Creation and Verification Using Blockchain;ioT and Machine Learning Algorithm in Smart Agriculture;RGB-to-Grayscale Conversion Using Truncated Floating-Point Multiplier.

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Virtual International conference on Futuristic Communication and Network Technologies, VICFCNT 2021

Virtual International Conference on Futuristic Communication...

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Virtual International conference on Futuristic Communication and Network Technologies, VICFCNT 2021

ISBN: (纸本)9789811983375

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Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration 20

Transmuter: Bridging the Efficiency Gap using Memory and Dat...

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ACM International conference on parallel architectures and compilation techniques (PACT)

作者： Pal, Subhankar Feng, Siying Park, Dong-hyeon Kim, Sung Amarnath, Aporva Yang, Chi-Sheng He, Xin Beaumont, Jonathan May, Kyle Xiong, Yan Kaszyk, Kuba Morton, John Magnus Sun, Jiawen O'Boyle, Michael Cole, Murray Chakrabarti, Chaitali Blaauw, David Kim, Hun-Seok Mudge, Trevor Dreslinski, Ronald Univ Michigan Ann Arbor MI 48109 USA Arizona State Univ Tempe AZ 85287 USA Univ Edinburgh Edinburgh Midlothian Scotland

ISBN: (纸本)9781450380751

With the end of Dennard scaling and Moore's law, it is becoming increasingly difficult to build hardware for emerging applications that meet power and performance targets, while remaining flexible and programmable for end users. This is particularly true for domains that have frequently changing algorithms and applications involving mixed sparse/dense data structures, such as those in machine learning and graph analytics. To overcome this, we present a flexible accelerator called Transmuter, in a novel effort to bridge the gap between General-Purpose Processors (GPPs) and Application-Specific Integrated Circuits (ASICs). Transmuter adapts to changing kernel characteristics, such as data reuse and control divergence, through the ability to reconfigure the on-chip memory type, resource sharing and dataflow at run-time within a short latency. This is facilitated by a fabric of light-weight cores connected to a network of reconfigurable caches and crossbars. Transmuter addresses a rapidly growing set of algorithms exhibiting dynamic data movement patterns, irregularity, and sparsity, while delivering GPU-like efficiencies for traditional dense applications. Finally, in order to support programmability and ease-of-adoption, we prototype a software stack composed of low-level runtime routines, and a high-level language library called TransPy, that cater to expert programmers and end-users, respectively. Our evaluations with Transmut er demonstrate average throughput (energy-efficiency) improvements of 5.0x (18.4x) and 4.2x (4.0x) over a high-end CPU and GPU, respectively, across a diverse set of kernels predominant in graph analytics, scientific computing and machine learning. Transmut er achieves energy-efficiency gains averaging 3.4x and 2.0x over prior FPGA and CGRA implementations of the same kernels, while remaining on average within 9.3x of state-of-the-art ASICs.

关键词： Reconfigurable architectures memory reconfiguration dataflow reconfiguration hardware acceleration general-purpose acceleration

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Load Balancing and parallel Computation Model for Performance and Accuracy over the Cluster of Nodes 2

Load Balancing and Parallel Computation Model for Performanc...

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2nd International conference on Innovative Practices in Technology and Management, ICIPTM 2022

作者： Vasuda, V. Srividya, K. Anusha, M. Vasavi College Of Engineering Hyderabad Telangana India

ISBN: (纸本)9781665466431

Cloud Computing can be online based network engineering which contributed with a rapid advancement at the progress of communication technological innovation by supplying assistance to clients of assorted conditions with aid from online computing sources. It's terms of hardware and software apps together side software growth testing and platforms applications because tools. Large-scale heterogeneous distributed computing surroundings give the assurance of usage of a huge quantity of computing tools in a comparatively low price. As a way to lessen the software development and setup onto such complicated surroundings, high speed parallel programming languages exist which have to be encouraged by complex operating techniques. There are numerous advantages for consumers in terms of cost and flexibility that come with Cloud computing's anticipated uptake. Building on well-established research in Internet solutions, networks and utility computing, virtualization et cetera Service-Oriented architectures and the Internet of Services (IoS) have implications for a wide range of technological issues such as parallel computing and load balancing as well as high availability and scalability. Effective load balancing methods are essential to solving these issues. Since such systems' size and complexity make it impossible to concentrate job execution on a few select servers, a parallel distributed solution is required. Adaptive task load model is the name of the method wesuggest in our article for balancing the workload (ATLM). We developed an adaptive parallel distributed computing paradigm as a result of this (ADPM). While still maintaining the model's integrity, ADPM employs a more flexible synchronization approach to cut down on the amount of time synchronous operations use. As well as the ATLM load balancing technique, which solves the straggler issue caused by the performance disparity between nodes, ADPM also applies it to ensure model correctness. The results indicate that

关键词： Application programs

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Compiling Chapel: Keys to Making parallel Programming Productive at Scale 20

Compiling Chapel: Keys to Making Parallel Programming Produc...

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ACM International conference on parallel architectures and compilation techniques (PACT)

作者： Chamberlain, Bradford L. Hewlett Packard Enterprise Seattle WA 98164 USA

ISBN: (纸本)9781450380751

Chapel is a parallel language designed to support productive programming from laptops to supercomputers. Unlike typical general-purpose approaches to large-scale computing, Chapel supports a global namespace and a global view of control. These make programming at scale more productive and natural by avoiding the need to utilize a Single Program, Multiple Data (SPMD) approach. Chapel is being developed as portable, open-source software and has demonstrated its ability to match or beat C/C++/MPI/OpenMP performance using code that's as easy to read as Python or Swift. In this talk, I will introduce some of Chapel's key features for those who are new to the language. However, most of the talk will focus on unique aspects of compiling Chapel. I will illustrate the transformations and analyses we use to implement Chapel's global view of data and control. I will also describe some optimizations that make use of Chapel's feature set to improve performance without sacrificing ease-of-use. In doing so, I will argue that when designed well, a productive language can enhance a compiler's ability to achieve performance and scalability rather than thwarting it. I'll wrap up by touching on some upcoming challenges for the Chapel compiler, including code generation for GPUs, reducing compilation time, and supporting interactive programming.

关键词： Chapel High Performance Computing Software Productivity

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Compact native code generation for dynamic languages on micro-core architectures 2021

Compact native code generation for dynamic languages on micr...

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30th ACM SIGPLAN International conference on Compiler Construction, CC 2021

作者： Jamieson, Maurice Brown, Nick EPCC University of Edinburgh Edinburgh United Kingdom

ISBN: (纸本)9781450383257

Micro-core architectures combine many simple, low memory, low power-consuming CPU cores onto a single chip. Potentially providing significant performance and low power consumption, this technology is not only of great interest in embedded, edge, and IoT uses, but also potentially as accelerators for data-center workloads. Due to the restricted nature of such CPUs, these architectures have traditionally been challenging to program, not least due to the very constrained amounts of memory (often around 32KB) and idiosyncrasies of the technology. However, more recently, dynamic languages such as Python have been ported to a number of micro-cores, but these are often delivered as interpreters which have an associated performance limitation. Targeting the four objectives of performance, unlimited code-size, portability between architectures, and maintaining the programmer productivity benefits of dynamic languages, the limited memory available means that classic techniques employed by dynamic language compilers, such as just-in-time (JIT), are simply not feasible. In this paper we describe the construction of a compilation approach for dynamic languages on micro-core architectures which aims to meet these four objectives, and use Python as a vehicle for exploring the application of this in replacing the existing micro-core interpreter. Our experiments focus on the metrics of performance, architecture portability, minimum memory size, and programmer productivity, comparing our approach against that of writing native C code. The outcome of this work is the identification of a series of techniques that are not only suitable for compiling Python code, but also applicable to a wide variety of dynamic languages on micro-cores. © 2021 ACM.

关键词： Python

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parallel Metaheuristics for Shop Scheduling: enabling Industry 4.0 2

Parallel Metaheuristics for Shop Scheduling: enabling Indust...

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2nd International conference on Industry 4.0 and Smart Manufacturing (ISM)

作者： Coelho, Pedro Silva, Cristovao Univ Coimbra Dept Mech Engn CEMMPRE P-3030788 Coimbra Portugal

Production scheduling is one of the most critical activities in manufacturing. Under the context of Industry 4.0 paradigm, shop scheduling becomes even more complex. Metaheuristics present the potential to solve these harder problems but demand substantial computational power. The use of high-performance parallel architectures, present in cloud computing and edge computing, may support the develop of better metaheuristics, enabling Industry 4.0 with solution techniques to deal with their scheduling complexity. This study provides an overview of parallel metaheuristics for shop scheduling in recent literature. We reviewed 28 papers and classified them, according to parallel architectures, shop configuration, metaheuristics and optimization criteria. The results support that parallel metaheuristic have potential to tackle Industry 4.0 scheduling problems. However, it is essential to extend the research to the cloud and edge computing, flexible shop configurations, dynamic problems with multi-resource, and multi-objective optimization. Future studies should consider the use of real-world data instances. (C) 2021 The Authors. Published by Elsevier B.V.

关键词： Industry 4.0 production scheduling metaheuristics parallel processing

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Compiling Pattern Matching to In-Place Modifications 2021

Compiling Pattern Matching to In-Place Modifications

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20th ACM SIGPLAN International conference on Generative Programming: Concepts and Experiences (GPCE)

作者： Iannetta, Paul Gonnord, Laure Radanne, Gabriel UCBL EnsL Univ Lyon CNRSInriaLIP Villeurbanne France Univ Grenoble Alpes Grenoble INP LCIS & LIP Grenoble France UCBL INRIA EnsL CNRSLIP Villeurbanne France

ISBN: (纸本)9781450391122

Algebraic data types and pattern matching are popular tools to build programs manipulating complex datastructures in a safe yet efficient manner. On top of its safety advantages, compilation techniques can turn pattern matching into highly efficient deconstruction code for immutable use cases. Conversely, high-performance datastructures and languages prefer to leverage (controlled) mutations to maximize time and memory efficiency. Algebraic data types provide a natural framework to efficiently describe in-place transformations as rewrite rules. Such representation could take advantage of parallelism opportunities that appear in tree-like structures. We present early steps towards a new technique to compile pattern matching as parallel in-place modifications of the underlying memory representation. Towards this goal, we combine the usual language approach which is common in pattern-matching compilation with tools from the polyhedral model, which is commonly used in high-performance code generation to output efficient C code. We present our formalism, along with a prototype implementation.

关键词： compilation ADT rewriting code generation

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parallel Execution Strategies for Cellular Automata on Shared Memory architectures 33

Parallel Execution Strategies for Cellular Automata on Share...

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33rd Euromicro International conference on parallel, Distributed, and Network-Based Processing, PDP 2025

作者： Giordano, Andrea De Rango, Alessio Mendicino, Giuseppe D'ambrosio, Donato Macri, Davide Rizzo, Luigi Rongo, Rocco Spataro, William ICAR-CNR Rende Italy University of Calabria Department of Environmental Engineering Italy University of Calabria Department of Mathematics and Computer Science Italy

ISBN: (纸本)9798331524937

Cellular Automata (CA) are extensively utilized for modeling and simulating complex systems due to their simplicity, flexibility, and ability to represent diverse phenomena. However, the computational intensity of CA models, particularly in large-scale applications, demands the development of efficient parallel execution techniques. This is especially critical when targeting shared memory architectures, where resource management and thread coordination play pivotal roles in achieving optimal performance. In this study, we examine a range of parallel execution strategies specifically designed to enhance the efficiency and scalability of CA models. The experimental evaluation highlights good scalability in execution time and resource utilization, making these strategies highly suitable for extensive simulations across various domains. Additionally, the results emphasize that imbalance conditions - often arising during CA computations - can considerably influence the effectiveness of choosing a given strategy. © 2025 IEEE.

关键词： Memory management

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Scalable Specialization: architectures, Interfaces, & Applications 20

Scalable Specialization: Architectures, Interfaces, & Applic...

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ACM International conference on parallel architectures and compilation techniques (PACT)

作者： Adve, Sarita, V Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)9781450380751

The end of Dennard scaling and Moore's law is driving transformational change in hardware, leading to a rise in specialized, domain-specific heterogeneous systems. There is an accompanying explosion of sophisticated applications deployed at the edge on diverse heterogeneous devices that interface directly with the end-user. Realizing the full potential of these trends will require new technologies for scalable specialization and a change in how we conduct systems research. First, we must move from evaluating single application components to end-to-end systems, replacing conventional power-performance-area metrics with those that capture end-user perception. Second, end-to-end system design requires moving from a focus on single accelerators to heterogeneous parallel systems with simultaneously communicating diverse accelerators, requiring scalable and specializable accelerator communication interfaces. Third, effective programmability of such systems requires new hardware-software interfaces designed to represent parallelism, heterogeneity, and communication. To illustrate the above shift, I will describe ILLIXR, the Illinois Extended Reality (XR) testbed, the first complete open-source XR system for enabling end-to-end systems research with a rich and demanding edge application domain; Spandex, a flexible and scalable accelerator communication interface that enables each accelerator to specialize for its coherence, consistency, and data movement requirements; and Heterogeneous parallel Virtual Memory (HPVM), a virtual ISA and compiler IR designed from the ground up as a hardware-software interface for heterogeneous parallel systems. I will summarize how these technologies are enabling ongoing projects towards scalable specialization.

关键词： Specialization heterogeneous parallelism accelerators extended reality hardware-software interfaces communication coherence

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