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Scalable Specialization: architectures, Interfaces, & Applications 20

Scalable Specialization: Architectures, Interfaces, & Applic...

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ACM International conference on parallel architectures and compilation techniques (PACT)

作者： Adve, Sarita, V Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)9781450380751

The end of Dennard scaling and Moore's law is driving transformational change in hardware, leading to a rise in specialized, domain-specific heterogeneous systems. There is an accompanying explosion of sophisticated applications deployed at the edge on diverse heterogeneous devices that interface directly with the end-user. Realizing the full potential of these trends will require new technologies for scalable specialization and a change in how we conduct systems research. First, we must move from evaluating single application components to end-to-end systems, replacing conventional power-performance-area metrics with those that capture end-user perception. Second, end-to-end system design requires moving from a focus on single accelerators to heterogeneous parallel systems with simultaneously communicating diverse accelerators, requiring scalable and specializable accelerator communication interfaces. Third, effective programmability of such systems requires new hardware-software interfaces designed to represent parallelism, heterogeneity, and communication. To illustrate the above shift, I will describe ILLIXR, the Illinois Extended Reality (XR) testbed, the first complete open-source XR system for enabling end-to-end systems research with a rich and demanding edge application domain; Spandex, a flexible and scalable accelerator communication interface that enables each accelerator to specialize for its coherence, consistency, and data movement requirements; and Heterogeneous parallel Virtual Memory (HPVM), a virtual ISA and compiler IR designed from the ground up as a hardware-software interface for heterogeneous parallel systems. I will summarize how these technologies are enabling ongoing projects towards scalable specialization.

关键词： Specialization heterogeneous parallelism accelerators extended reality hardware-software interfaces communication coherence

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Source Code Classification for Energy Efficiency in parallel Ultra Low-Power Microcontrollers

Source Code Classification for Energy Efficiency in Parallel...

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Design, Automation and Test in Europe conference and Exhibition (DATE)

作者： Parisi, Emanuele Barchi, Francesco Bartolini, Andrea Tagliavini, Giuseppe Acquaviva, Andrea DEI Univ Bologna Bologna Italy

ISBN: (纸本)9783981926354

The analysis of source code through machine learning techniques is an increasingly explored research topic aiming at increasing smartness in the software toolchain to exploit modern architectures in the best possible way. In the case of low-power, parallel embedded architectures, this means finding the configuration, for instance in terms of the number of cores, leading to minimum energy consumption. Depending on the kernel to be executed, the energy optimal scaling configuration is not trivial. While recent work has focused on general-purpose systems to learn and predict the best execution target in terms of the execution time of a snippet of code or kernel (e.g. offload OpenCL kernel on multicore CPU or GPU), in this work we focus on static compile-time features to assess if they can be successfully used to predict the minimum energy configuration on PULP, an ultra-low-power architecture featuring an on-chip cluster of RISC-V processors. Experiments show that using machine learning models on the source code to select the best energy scaling configuration automatically is viable and has the potential to be used in the context of automatic system configuration for energy minimisation.

关键词： Static Code Analysis Machine Learning OpenMP Energy Efficiency parallel Low-Power Embedded Systems

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compilation of SQL Queries for Efficient Distributed In-Memory Processing 23

Compilation of SQL Queries for Efficient Distributed In-Memo...

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proceedings of the 33rd Annual International conference on Computer Science and Software Engineering

作者： Chatterjee Sudip Sharma Shubh Ivan Nithin Verma Saumya Ray Suprio Stoodley Mark Zuzarte Calisto Finlay Ian University of New Brunswick Fredericton New Brunswick Canada IBM Markham Ontario Canada

A query processing engine is the core component of any modern database system. There are several types of query processing en-gines that employ different query processing techniques. The speed of data-driven decision-making and analytics is crucial to organi-zations that build software and system applications. An intuitive way to speed up database querying is to improve the performance of these engines. Conventionally, databases use a disk-oriented, pull-based or tuple-at-a-time interpreted query evaluation model. This paper introduces a compilation-based, in-memory query pro-cessing engine CasaDB that accepts an SQL query and generates distributed C++ (UPC++) based physical query plans. As part of this work, different models and components of query processing are explored, and efficient Partitioned Global Address Space (PGAS) based parallel programs corresponding to SQL queries are designed and developed, emitted by a code generator that uses a data-centric compilation strategy. The approach proposed in this paper com-bines high-performance parallel programs with database query processing to take advantage of the advances in hardware available. We conduct an extensive experimental evaluation with industry-standard TPC-H benchmark. Our experimental evaluation shows that 4-node query execution produces up to 5× speedup in query performance over single-node approaches.

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30th International conference on parallel and Distributed Processing techniques, PDPTA 2024, held as part of the World Congress in Computer Science, Computer Engineering and Applied Computing, CSCE 2024

30th International Conference on Parallel and Distributed Pr...

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30th International conference on parallel and Distributed Processing techniques, PDPTA 2024, held as part of the World Congress in Computer Science, Computer Engineering and Applied Computing, CSCE 2024

ISBN: (纸本)9783031856372

The proceedings contain 24 papers. The special focus in this conference is on parallel and Distributed Processing techniques. The topics include: parallel N-Body Performance Comparison: Julia, Rust, and More;REFT: Resource-Efficient Federated Training Framework for Heterogeneous and Resource-Constrained Environments;An Efficient Data Provenance Collection Framework for HPC I/O Workloads;using Minicasts for Efficient Asynchronous Causal Unicast and Byzantine Tolerance;a Comparative Study of Two Matrix Multiplication Algorithms Under Current Hardware architectures;Is Manual Code Optimization Still Required to Mitigate GPU Thread Divergence? Applying a Flattening Technique to Observe Performance;towards Automatic, Predictable and High-Performance parallel Code Generation;Attack Graph Generation on HPC Clusters;analyzing the Influence of File Formats on I/O Patterns in Deep Learning;inference of Cell–Cell Interactions Through Spatial Transcriptomics Data Using Graph Convolutional Neural Networks;natural Product-Like Compound Generation with Chemical Language Models;improved Early–Modern Japanese Printed Character Recognition Rate with Generated Characters;Improved Method for Similar Music Recommendation Using Spotify API;Reconfigurable Virtual Accelerator (ReVA) for Large-Scale Acceleration Circuits;Building Simulation Environment of Reconfigurable Virtual Accelerator (ReVA);vector Register Sharing Mechanism for High Performance Hardware Acceleration;Efficient Compute Resource Sharing of RISC-V Packed-SIMD Using Simultaneous Multi-threading;introducing Competitive Mechanism to Differential Evolution for Numerical Optimization;hyper-heuristic Differential Evolution with Novel Boundary Repair for Numerical Optimization;jump Like a Frog: Optimization of Renewable Energy Prediction in Smart Gird Based on Ultra Long Term Network;vision Transformer-Based Meta Loss Landscape Exploration with Actor-Critic Method;Fast Computation Method for Stopping Condition of Range Restricted

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Efficient and Scalable AIxeleration of Reactive CFD Solvers Coupled with Deep Learning Inference on Heterogeneous architectures

Efficient and Scalable AIxeleration of Reactive CFD Solvers ...

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proceedings of the 2025 International conference on High Performance Computing in Asia-Pacific Region Workshops

作者： Fabian Orland Ludovico Nista Nick Kocher Joris Vanvinckenroye Heinz Pitsch Christian Terboven High Performance Computing RWTH Aachen University Aachen Germany Institute for Combustion Technology RWTH Aachen University Aachen Germany Chair of AI Methodology RWTH Aachen University Aachen Germany

ISBN: (纸本)9798400713422

The convergence of high-performance computing (HPC) and artificial intelligence (AI) is transforming numerical simulations across various scientific domains. In reactive flow simulations, deep learning (DL) techniques, are emerging as promising alternatives to traditional closure models in large eddy simulations (LES). Although a priori investigations -where models are tested on pre-existing datasets - have demonstrated remarkable performance, a posteriori investigations - which assess model behavior within a running simulation - remain crucial to ensuring stability and accuracy. To bridge this gap, seamless integration between computational fluid dynamics (CFD) solvers and widely used DL frameworks, such as PyTorch or TensorFlow is required. However, traditional CFD solvers are highly optimized for CPU execution, whereas DL inference benefits from acceleration on GPUs or other specialized hardware. This architectural mismatch presents a significant challenge in efficiently leveraging modern heterogeneous HPC platforms. To address this issue, we introduce AIxeleratorService, an open-source C++ library designed to enable efficient deployment of DL models within highly parallel CFD solvers running on heterogeneous architectures. Additionally, we present a Fortran ML module that integrates AIxeleratorService, providing users of Fortran-based CFD solvers with a streamlined, end-to-end workflow for incorporating trained DL architectures into their simulations. We validate our approach by coupling AIxeleratorService with our in-house CFD solver, CIAO, and applying it to two LES configurations. In one, a super-resolution generative adversarial network (SRGAN) reconstructs the unresolved Reynolds stresses tensor to correctly account for the momentum energy transport. On the other, a UNet-type architecture computes the source term of the progress variable equation, which is essential for accurately describing the chemical reaction rate and flame propagation in turbulent comb

关键词： CFD

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Fast and Scalable Sparse Triangular Solver for Multi-GPU Based HPC architectures 21

Fast and Scalable Sparse Triangular Solver for Multi-GPU Bas...

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50th International conference on parallel Processing (ICPP)

作者： Xie, Chenhao Chen, Jieyang Firoz, Jesun Li, Jiajia Song, Shuaiwen Leon Barker, Kevin Raugas, Mark Li, Ang Pacific Northwest Natl Lab Richland WA 99352 USA Oak Ridge Natl Lab Oak Ridge TN USA Univ Sydney Sydney NSW Australia William & Mary Williamsburg VA USA

ISBN: (纸本)9781450390682

Designing efficient and scalable sparse linear algebra kernels on modern multi-GPU based HPC systems is a challenging task due to significant irregular memory references and workload imbalance across GPUs. These challenges are particularly compounded in the case of Sparse Triangular Solver (SpTRSV), which introduces additional complexity of two-dimensional computation dependencies among subsequent computation steps. Dependency information may need to be exchanged and shared among GPUs, thus warranting for efficient memory allocation, data partitioning, and workload distribution as well as fine-grained communication and synchronization support. In this work, we focus on designing algorithm for SpTRSV in a single-node, multi-GPU setting. We demonstrate that directly adopting unified memory can adversely affect the performance of SpTRSV on multi-GPU architectures, despite linking via fast interconnect like NVLinks and NVSwitches. Alternatively, we employ the latest NVSHMEM technology based on Partitioned Global Address Space programming model to enable efficient finegrained communication and drastic synchronization overhead reduction. Furthermore, to handle workload imbalance, we propose a malleable task-pool execution model which can further enhance the utilization of GPUs. By applying these techniques, our experiments on the NVIDIA multi-GPU supernode V100-DGX-1 and DGX-2 systems demonstrate that our design can achieve an average of 3.53x (up to 9.86x) speedup on a DGX-1 system and 3.66 x (up to 9.64x) speedup on a DGX-2 system with four GPUs over the Unified-Memory design. The comprehensive sensitivity and scalability studies also show that the proposed zero-copy SpTRSV is able to fully utilize the computing and communication resources of the multi-GPU systems.

关键词： Sparse Linear Algebra Kernels Triangular Solver Multi-GPU Systems Task Model

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23rd International conference on Formal Engineering Methods, ICFEM 2022

23rd International Conference on Formal Engineering Methods,...

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23rd International conference on Formal Engineering Methods, ICFEM 2022

ISBN: (纸本)9783031172434

The proceedings contain 25 papers. The special focus in this conference is on Formal Engineering Methods. The topics include: PFMC: A parallel Symbolic Model Checker for Security Protocol Verification;a Formal Methodology for Verifying Side-Channel Vulnerabilities in Cache architectures;refined Modularization for Bounded Model Checking Through Precondition Generation;TTT/ik: Learning Accurate Mealy Automata Efficiently with an Imprecise Symbol Filter;a Proof System for Cyber-Physical Systems with Shared-Variable Concurrency;theorem Proving for Maude Specifications Using Lean;on How to Not Prove Faulty Controllers Safe in Differential Dynamic Logic;declassification Predicates for Controlled Information Release;trace Refinement in B and Event-B;canonical Narrowing for Variant-Based Conditional Rewrite Theories;model Checking B Models via High-Level Code Generation;on Probabilistic Extension of the Interaction Theory;extracting Weighted Finite Automata from Recurrent Neural Networks for Natural Languages;roboCert: Property Specification in Robotics;formally Verified Animation for RoboChart Using Interaction Trees;machine-Checked Executable Semantics of Stateflow;modular Analysis of Tree-Topology Models;non-linear Optimization Methods for Learning Regular Distributions;separation of Concerning Things: A Simpler Basis for Defining and Programming with the C/C++ Memory Model;creusot: A Foundry for the Deductive Verification of Rust Programs;generation of a Reversible Semantics for Erlang in Maude;program Slicing techniques with Support for Unconditional Jumps;Formal Verification of the Inter-core Synchronization of a Multi-core RTOS Kernel.

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TransMixer: A Hybrid Transformer and CNN Architecture for Polyp Segmentation

TransMixer: A Hybrid Transformer and CNN Architecture for Po...

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2022 IEEE International conference on Bioinformatics and Biomedicine, BIBM 2022

作者： Huang, Yanglin Tan, Donghui Zhang, Yuan Li, Xuanya Hu, Kai Xiangtan University Key Laboratory of Intelligent Computing and Information Processing of Ministry of Education Xiangtan411105 China Affiliated Hospital of Xiangnan University Chengzhou423000 China Baidu Inc Beijing100085 China Xiangnan University Key Laboratory of Medical Imaging and Artificial Intelligence of Hunan Province Chenzhou423000 China

ISBN: (纸本)9781665468190

Learning how to fully extract global representations and local features is a key factor in improving the performance of polyp segmentation. In this paper, we explore the potential of combined techniques of Transformers and convolutional neural networks (CNNs) to address the challenges of polyp segmentation. Specifically, we present TransMixer, a hybrid interaction fusion architecture of the Transformer branch and the CNN branch, which is able to enhance the local details of global representations and the global context awareness of local features. To achieve this, we first bridge the semantic gap between the Transformer branch and the CNN branch through the Interaction Fusion Module (IFM), and then make full use of both respective properties to enhance polyp feature representations. After that, we further propose the Hierarchical Attention Module (HAM) to collect polyp semantic information from high-level features to gradually guide the recovery of polyp spatial information in low-level features. Quantitative and qualitative results show that the proposed model is more robust to various complex situations compared to existing methods, and achieves state-of-the-art performance in polyp segmentation. © 2022 IEEE.

关键词： parallel architectures

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PathSeeker: a fast mapping algorithm for CGRAs 22

PathSeeker: a fast mapping algorithm for CGRAs

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proceedings of the 2022 conference & Exhibition on Design, Automation & Test in Europe

作者： Mahesh Balasubramanian Aviral Shrivastava Arizona State University

ISBN: (纸本)9783981926361

Coarse-grained reconfigurable arrays (CGRAs) have gained traction over the years as a low-power accelerator due to the efficient mapping of the compute-intensive loops onto the 2-D array by the CGRA compiler. When encountering a mapping failure for a given node, existing mapping techniques either exit and retry the mapping anew, or perform backtracking, i.e., recursively remove the previously mapped node to find a valid mapping. Abandoning mapping and starting afresh can deteriorate the quality of mapping and the compilation time. Even backtracking may not be the best choice since the previous node may not be the incorrectly placed node. To tackle this issue, we propose PathSeeker - a mapping approach that analyzes mapping failures and performs local adjustments to the schedule to obtain a mapping. Experimental results on 35 top performance-critical loops from MiBench, Rodinia, and Parboil benchmark suites demonstrate that PathSeeker can map all of them with better mapping quality and dramatically less compilation time than the previous state-of-the-art approaches - GraphMinor and RAMP, which were unable to map 20 and 5 loops, respectively. Over these benchmarks, PathSeeker achieves 28% better performance at 550x compilation speedup over GraphMinor and 3% better performance at 10x compilation speedup over RAMP on a 4X4 CGRA.

关键词： compilers CGRA reconfigurable architectures mapping

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Smart techniques for Flying-probe Testing 16

Smart Techniques for Flying-probe Testing

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16th International conference on Software Technologies (ICSOFT)

作者： Calabrese, Andrea Quer, Stefano Squillero, Giovanni Politecn Torino Dept Control & Comp Engn DAUIN Turin Italy

ISBN: (纸本)9789897585234

In the production of printed circuit boards, in-circuit tests verify whether the electric and electronic components of the board have been correctly soldered. When the test is performed using flying-probes, several probes are simultaneously moved on the board to reach and touch multiple test points. Taking into consideration the layout of the board, the characteristics of the tester, and several other physical constraints, not all movements of the probes are mutually compatible nor they can always be performed through simple straight lines. As the cost of the test is mainly related to its length, and patching the path of one probe may create new incompatibilities with the trajectory of the other probes, one should carefully trade off the time required to find the trajectories with the time required by the probes to follow them. In this paper, we model the movements of our flying probes as a multiple and collaborative planning problem. We describe an approach for detecting invalid movements and we design a strategy to correct them with the addition of new intermediate points in the trajectory. We report the entire high-level procedure and we explore the optimizations performed in the more expensive and complex steps. We also present parallel implementations of our algorithms, either relying on multi-core CPU devices or many-cores GPU platforms, when these units may be useful to achieve greater speedups. Experimental results show the effectiveness of the proposed solution in terms of elapsed computation times.

关键词： Algorithms Algorithm Design and Analysis Testing Graph Theory parallel architectures

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