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Continuous Program Optimization via Advanced Dynamic compilation techniques 2019

Continuous Program Optimization via Advanced Dynamic Compila...

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10th Workshop on parallel Programming and Run-Time Management techniques for Many-Core architectures / 8th Workshop on Design Tools and architectures For Multicore Embedded Computing Platforms (PARMA-DITAM)

作者： Festa, Marco Gervasoni, Nicole Cherubin, Stefano Agosta, Giovanni Politecn Milan DEIB Milan Italy

ISBN: (纸本)9781450363211

In High Performance Computing, it is often useful to fine tune an application code via recompilation of specific computational intensive code fragments to leverage runtime knowledge. Traditional compilers rarely provide such capabilities, while solutions such as LIBVC allow C/C++ code to employ dynamic compilation. We evaluate the impact of the introduction of Just-in-Time (JIT) compilation in a framework supporting partial dynamic (re-) compilation of functions to provide continuous optimization in high performance environments. We show that JIT solutions can have comparable performance in terms of code quality and smaller compilation overhead w.r.t. the libVC alternatives. We further demonstrate the strength of our approach against a state-of-the-art interpreter-based dynamic evaluation solution.

关键词： Dynamic compilation JIT Continuous Program Optimization

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BOLT: Optimizing OpenMP parallel Regions with User-Level Threads 28

BOLT: Optimizing OpenMP Parallel Regions with User-Level Thr...

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28th International conference on parallel architectures and compilation techniques (PACT)

作者： Iwasaki, Shintaro Amer, Abdelhalim Taura, Kenjiro Seo, Sangmin Balaji, Pavan Univ Tokyo Tokyo Japan Argonne Natl Lab Lemont IL USA

ISBN: (纸本)9781728136134

OpenMP is widely used by a number of applications, computational libraries, and runtime systems. As a result, multiple levels of the software stack use OpenMP independently of one another, often leading to nested parallel regions. Although exploiting such nested parallelism is a potential opportunity for performance improvement, it often causes destructive performance with leading OpenMP runtimes because of their reliance on heavyweight OS-level threads. User-level threads (ULTs) are more lightweight alternatives but existing ULT-based runtimes suffer from several shortcomings: 1) thread management costs remain significant and outweigh the benefits from additional parallelism;2) the shift to ULTs often hurts the more common flat parallelism case;and 3) absence of user control over thread-to-CPU binding, a critical feature on modern systems. This paper presents BOLT, a practical ULT-based OpenMP runtime system that efficiently supports both flat and nested parallelism. This is accomplished on three fronts: 1) advanced data reuse and thread synchronization strategies;2) thread coordination that adapts to the level of oversubscription;and 3) an implementation of the modern OpenMP thread-to-CPU binding interface tailored to ULT-based runtimes. The result is a highly optimized runtime that transparently achieves similar performance compared with leading state-of-the-art widely used OpenMP runtimes under flat parallelism, while outperforming all existing runtimes under nested parallelism.

关键词： Multithreading Runtime Systems OpenMP User-Level Threads

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proceedings of the 46th International conference on Very Large Data Bases, VLDB January 2020

Proceedings of the 46th International Conference on Very Lar...

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46th International conference on Very Large Data Bases, VLDB 2020

This proceedings contains 14 papers. The proceedings of the VLDB Endowment (PVLDB) provides a high-quality publication service to the data management research community. This conference issue focuses on the breadth of the data management field. The topics include view updates, query compilation, concurrency control, data parsing, data cleaning;tackle more recent problems in particular graph processing;on road networks;failure handling techniques from data processing to distributed application programming;breadth of technical problems as well as the breadth of solutions spanning the hardware-software stack and going from theoretical to systems-oriented are an important quality of the database;etc. The key terms of this proceedings include dynamic road networks, massively parallel parsing, contended main-memory multicore transactions, LSH framework, homogeneous network embedding, data cleaning, MDedup, debuggable dataflow system, dynamic speculative optimizations, imputation of missing values techniques.

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A Methodology for Characterizing Sparse Datasets and Its Application to SIMD Performance Prediction 28

A Methodology for Characterizing Sparse Datasets and Its App...

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28th International conference on parallel architectures and compilation techniques (PACT)

作者： Zhu, Gangyi Jiang, Peng Agrawal, Gagan Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA

ISBN: (纸本)9781728136134

Irregular computations are commonly seen in many scientific and engineering domains that use unstructured meshes or sparse matrices. The performance of an irregular application is very dependent upon the dataset. This paper poses the following question: "given an unstructured mesh or a graph,what method(s) can be used to sample it, such that the execution on the resulting sampled dataset can accurately reflect performance characteristics on the full dataset". Our first insight is that developing a universal sampling approach for all sparse matrices is unpractical. According to the non-zero distribution of the sparse matrix, we propose two novel sampling strategies: Stride Average sampling and Random Tile sampling, which are suitable for uniform and skewed sparse matrices respectively. To help categorize a sparse matrix as uniform or skewed, we introduce clustering coefficient as an important feature which can be propagated into the decision tree model. We also adapt Random Node Neighbor sampling approach for efficient estimation of clustering coefficient. We apply our unstructured dataset characterization approach to modeling the performance for SIMD irregular applications, where the sampled dataset obtained is used to predict cache miss rate and SIMD utilization ratio. We also build analytical models to estimate overheads incurred by load imbalance among threads. With knowledge of these factors, we adapt a code skeleton framework SKOPE to capture the workload behaviors and aggregate performance statistics for execution time prediction.

关键词： Sparse matrices parallel processing Adaptation models Instruction sets Load modeling Predictive models Analytical models

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Deepframe: A Profile-driven Compiler for Spatial Hardware Accelerators 28

Deepframe: A Profile-driven Compiler for Spatial Hardware Ac...

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28th International conference on parallel architectures and compilation techniques (PACT)

作者： Guha, Apala Vedula, Naveen Shriraman, Arrvindh Simon Fraser Univ Sch Comp Sci Burnaby BC Canada

ISBN: (纸本)9781728136134

Tracing code paths to form extended basic blocks is useful in many areas, compiler optimizations [1], improving instruction cache behavior [2] and custom-hardware offloading [3]. Prior work has been plagued by small traces, limited either by the overheads of dynamic profiling, statically available information [4], or side-exit branches [5]. In this work, we rethink what code path sequences to fuse and construct long traces for offloading to spatial accelerators, while minimizing the occurrence of side exits which limit dynamic coverage. We introduce a novel technique that recasts learning a program's execution patterns as a natural-language-processing problem, CBOW (Continuous Bag of Words). We then use a deep learning network to learn the relationships among paths. During the compilation phase, the compiler uses a sequence miner to decide what paths are likely to occur. The learning network predicts a Deepframe online, which is an extended basic block comprising a multi-path sequence (each path itself is composed of multiple basic blocks). We demonstrate the efficacy of Deepframe on spatial hardware accelerators and find the following: i) Deepframe can construct up to 5x (max: 27x) longer offload regions compared to prior approaches. ii) Surprisingly far-flung ILP (instruction-level parallelism) and MLP (memory-level parallelism) can be mined from the frames statically (5.5x increase in ILP and 10.5x increase in MLP). iii) The frames offloaded to the spatial accelerator have minimal side exits (mis-speculation) and achieve sufficient dynamic coverage to improve overall application performance (up to 9x improvement). We will be releasing open-source our end-to-end compiler prototype based on LLVM.

关键词： Hardware parallel processing History Out of order Deep learning Optimization

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Reducing Data Movement and Energy in Multilevel Cache Hierarchies without Losing Performance: Can you have it all? 28

Reducing Data Movement and Energy in Multilevel Cache Hierar...

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28th International conference on parallel architectures and compilation techniques (PACT)

作者： Wang, Jiajun Ramrakhyani, Prakash Elsasser, Wendy John, Lizy Kurian Univ Texas Austin Austin TX 78712 USA Arm Res Austin TX USA

ISBN: (纸本)9781728136134

Optimizing a multilayer cache hierarchy involves a careful balance of data placement, replacement, promotion, bypassing, prefetching, etc. to capture the various properties of access streams. Often getting good performance involves aggressively orchestrating the movement of the data to be available at the appropriate layers of the cache hierarchy at appropriate times. However, it has been popularly recognized that aggressive movement of data results in high energy consumption. State-of-the-art caching policies such as Hawkeye and MPPPB yield excellent performance but incur more data movement compared to policies such as CHAR, and Flexclusion. Considering the energy cost of data movement, we architect a FILtered Multi-level (FILM) caching policy, which yields good performance with reduced levels of data movement. It achieves this by identifying appropriate cache layers for each block of data using a bloom filter and table based predictors. The bloom filter helps to overcome the challenges associated with capturing PC-based information in exclusive caches in an efficient manner. When there is free space in the bypassed cache layer, FILM overrides the initial prediction and allows cache block installation into the cache level achieving more low latency hits. FILM also incorporates an explicit mechanism for handling prefetches, which allows it to train differently for data from demand requests versus prefetch requests. By incorporating quick detection and correction of stale/incorrect bypass decisions, FILM significantly reduces cache block installations and data movement, resulting in up to 10% reduction in dynamic energy at the LLC and DRAM compared with Hawkeye EX or MPPPB EX. Considering energy-delay product as a metric, FILM is 10%, 11%, and 5% better than Hawkeye EX, MPPPB EX, and CHAR respectively.

关键词： Prefetching Random access memory Hardware Training Microprocessors parallel architectures

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SWMapper: Scalable Read Mapper on SunWay TaihuLight 20

SWMapper: Scalable Read Mapper on SunWay TaihuLight

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49th International conference on parallel Processing (ICPP)

作者： Xu, Kai Duan, Xiaohui Meng, Xiangxu Li, Xin Schmidt, Bertil Liu, Weiguo Shandong Univ Sch Software Jinan Peoples R China Natl Supercomp Ctr Wuxi Jiangsu Peoples R China Shandong Univ Sch Software Minist Educ Engn Res Ctr Digital Media Technol Jinan Peoples R China Johannes Gutenberg Univ Mainz Mainz Germany

ISBN: (纸本)9781450388160

With the rapid development of next-generation sequencing (NGS) technologies, high throughput sequencing platforms continuously produce large amounts of short read DNA data at low cost. Read mapping is a performance-critical task, being one of the first stages required for many different types of NGS analysis pipelines. We present SWMapper - a scalable and efficient read mapper for the Sunway TaihuLight supercomputer. A number of optimization techniques are proposed to achieve high performance on its heterogeneous architecture which are centered around a memory-efficient succinct hash index data structure including seed filtration, duplicate removal, dynamic scheduling, asynchronous data transfer, and overlapping I/O and computation. Furthermore, a vectorized version of the banded Myers algorithm for pairwise alignment with 256-bit vector registers is presented to fully exploit the computational power of the SW26010 processor. Our performance evaluation shows that SWMapper using all 4 compute groups of a single Sunway TaihuLight node outperforms S-Aligner on the same hardware by a factor of 6.2. In addition, compared the state-of-the-art CPU-based mappers RazerS3, BitMapper2, and Hobbes3 running on a 4-core Xeon W-2123v3 CPU, SWMapper achieves speedups of 26.5, 7.8, and 2.6, respectively. Our optimizations achieve an aggregated speedup of 11 compared to the naive implementation on one compute group of an SW26010 processor as well as a strong scaling efficiency of 74% on 128 compute groups.

关键词： bioinformatics read mapping Sunway TailhuLight heterogeneous architectures

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Energy efficiency evaluation of parallel execution of devs models in multicore architectures 20

Energy efficiency evaluation of parallel execution of devs m...

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proceedings of the Winter Simulation conference

作者： Guillermo G. Trabes Veronica Gil Costa Gabriel A. Wainer Carleton University and Universidad Nacional de San Luis Ottawa CANADA Universidad Nacional de San Luis San Luis ARGENTINA Carleton University Ottawa CANADA

ISBN: (纸本)9781728194998

Complex models in science and engineering need better techniques to execute simulations efficiently. As we need high performance computers with many processors and memory to execute complex simulations faster, we face a problem with the consumption of energy. Therefore, we need new ways to define efficiency in simulations, measured not only in terms of computation time, but in terms of the amount of energy required to execute them. The Discrete-Event System Specification (DEVS) formalism, a well-known technique for modeling and simulation, includes simulation algorithms that allow running DEVS models in parallel computers. Nevertheless, no studies exist on the execution of DEVS simulations on parallel computers efficiently in terms of energy use. In this work, we show an energy efficiency evaluation of the execution of DEVS simulations on a shared-memory multicore architecture. The results presented show that executing in parallel can improve energy efficiency in these architectures.

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Rumor Has It: Optimizing the Belief Propagation Algorithm for parallel Processing 20

Rumor Has It: Optimizing the Belief Propagation Algorithm fo...

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49th International conference on parallel Processing (ICPP)

作者： Trotter, Michael Wood, Timothy Huang, H. Howie George Washington Univ Washington DC 20052 USA

ISBN: (纸本)9781450388689

By modelling how the probability distributions of individuals' states evolve as new information flows through a network, belief propagation has broad applicability ranging from image correction to virus propagation to even social networks. Yet, its scant implementations confine themselves largely to the realm of small Bayesian networks. Applications of the algorithm to graphs of large scale are thus unfortunately out of reach. To promote its broad acceptance, we enable belief propagation for both small and large scale graphs utilizing GPU processing. We therefore explore a host of optimizations including a new simple yet extensible input format enabling belief propagation to operate at massive scale, along with significant workload processing updates and meticulous memory management to enable our implementation to outperform prior works in terms of raw execution time and input size on a single machine. Utilizing a suite of parallelization technologies and techniques against a diverse set of graphs, we demonstrate that our implementations can efficiently process even massive networks, achieving up to nearly 121x speedups versus our control yet optimized single threaded implementations while supporting graphs of over ten million nodes in size in contrast to previous works' support for thousands of nodes using CPU-based multi-core and host solutions. To assist in choosing the optimal implementation for a given graph, we provide a promising method utilizing a random forest classifier and graph metadata with a nearly 95% F1-score from our initial benchmarking and is portable to different GPU architectures to achieve over an F1-score of over 72% accuracy and a speedup of nearly 183x versus our control running in this new environment.

关键词： GPGPU parallelization graph processing parallel processing Bayesian Networks Markov Random Fields

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ACM International conference Proceeding Series

ACM International Conference Proceeding Series

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10th Workshop on parallel Programming and Run-Time Management techniques for Many-Core architectures and 8th Workshop on Design Tools and architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2019

ISBN: (纸本)9781450363211

The proceedings contain 4 papers. The topics discussed include: OpenMP and critical real-time systems: a possible union?;efficient architectures for machine learning systems;tuning DSE for heterogeneous multi-processor embedded systems by means of a self-equalized weighted sum method;and continuous program optimization via advanced dynamic compilation techniques.

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