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NavCim: Comprehensive Design Space Exploration for Analog Computing-in-Memory architectures 24

NavCim: Comprehensive Design Space Exploration for Analog Co...

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International conference on parallel architectures and compilation techniques (PACT)

作者： Park, Juseong Kim, Boseok Sung, Hyojin Pohang Univ Sci & Technol Pohang South Korea Seoul Natl Univ Seoul South Korea

ISBN: (数字)9798400706318

ISBN: (纸本)9798400706318

Analog computing-in-memory (ACiM) technology has shown strong potential for neural network accelerators, addressing von-Neumann performance bottlenecks with in-memory data processing and computation. Understanding the ACiM design space, including its trade-offs and constraints, and systematically and effectively exploring it for optimal performance is essential to turn the promise into a viable product. Recent research demonstrated that multi-objective searches for ACiM architectures with heterogeneous tiles can simultaneously optimize power, performance, and area (PPA), outperforming existing tiled ACiM proposals. In this paper, we propose NavCim, a comprehensive ACiM design space exploration mechanism that advances the prior work in terms of search efficiency, search space coverage, and optimization metrics. NavCim introduces predictive modeling of ACiM hardware performance and uses the PPA prediction models instead of running simulators, significantly reducing search overheads. Faster searches enable NavCim to extend the architecture and model search spaces with an evolutionary search process to optimize architectures with more than two different tile sizes for multiple input models. With accuracy-aware searches, NavCim considers PPA and model accuracy together as optimization goals to achieve more balanced trade-offs. The experimental searches show that NavCim leverages predictive models to reduce search time by up to 7.3x without compromising the quality of search results. It also successfully identifies heterogeneous ACiM architectures that can efficiently execute multiple models on a single chip, improving accuracy by up to 19% over the prior work.

关键词： Accuracy Neural networks Predictive models Extraterrestrial measurements Data processing Hardware Space exploration parallel architectures Proposals Optimization

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vSPACE: Supporting parallel Network Packet Processing in Virtualized Environments through Dynamic Core Management 24

vSPACE: Supporting Parallel Network Packet Processing in Vir...

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International conference on parallel architectures and compilation techniques (PACT)

作者： Park, Gyeongseo Kim, Minho Kang, Ki-Dong Jeon, Yunhyeong Kim, Sungju Kim, Hyosang Kim, Daehoon DGIST ETRI Daegu South Korea DGIST Daegu South Korea ETRI Daejeon South Korea Yonsei Univ Seoul South Korea

ISBN: (数字)9798400706318

ISBN: (纸本)9798400706318

Data centers face significant performance challenges with parallel processing for network I/O in virtualized environments, particularly for latency-critical (LC) workloads that must satisfy strict Service Level Objectives (SLOs). While previous studies have addressed performance challenges in network I/O virtualization, they overlook the impact of excessive parallelism on the performance of Virtual Machines (VMs). We observe that excessive parallelization for VMs and network I/O processing can lead to core oversubscription, resulting in significant resource contention, frequent preemptions, and task migrations. Based on these observations, we propose vSPACE, dynamic core management specifically designed to support parallel network I/O processing in virtualized environments efficiently. To reduce scheduling contention, vSPACE creates distinct core allocation groups for VM and network I/O and assigns dedicated cores to each. Then, it dynamically adjusts the number of allocated cores to enforce appropriate parallelism for VMs and network I/O processing based on varying demands. vSPACE employs continuous monitoring and a heuristic algorithm to periodically determine appropriate core allocation, addressing excessive contention and improving energy and resource efficiency. vSPACE operates in three modes: performance improvement, energy efficiency, and resource efficiency. Our evaluations demonstrate that vSPACE significantly enhances throughput by up to 4.2x compared to existing core allocation approaches and improves energy and resource efficiency by up to 16.5% and 30.5%, respectively.

关键词： Data centers parallel processing Dynamic scheduling Throughput Energy efficiency Virtual machines parallel architectures Resource management Monitoring Faces

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Activation Sequence Caching: High-Throughput and Memory-Efficient Generative Inference with a Single GPU 24

Activation Sequence Caching: High-Throughput and Memory-Effi...

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International conference on parallel architectures and compilation techniques (PACT)

作者： Kim, Sowoong Sim, Eunyeong Shin, Youngsam Cho, YeonGon Baek, Woongki UNIST Ulsan South Korea Samsung Adv Inst Technol Suwon South Korea

ISBN: (数字)9798400706318

ISBN: (纸本)9798400706318

Generative artificial intelligence is widely used for various tasks such as language translation and art creation. Generative inference employs the key and value tensors to encode relational information among the tokens in the input and output sequences. Most of the existing generative inference frameworks use KV caching (KVC), which caches the key and value tensors (i.e., the KV cache) to avoid recomputing the key and value tensors for each of the processed tokens. Despite the widespread use of KVC, in-depth characterization of KVC with tensor offloading, which enables generative inference with a single GPU, remains yet to be explored. To bridge this gap, this work presents an in-depth characterization study of KVC, which demonstrates that KVC makes a suboptimal trade-off between computations and communications in the context of generative inference with tensor offloading. Guided by the characterization results, we propose a novel caching technique called activation sequence caching (ASC) for high-throughput and memory-efficient generative inference with a single GPU. ASC is designed to significantly reduce the memory usage and communication overheads of generative inference at the cost of the increased computational complexity. We provide an analytical analysis of the three caching techniques (i.e., zero caching, KVC, and ASC) for generative inference in terms of the memory usage, communication overheads, and computational complexity. Our quantitative evaluation demonstrates the effectiveness of ASC in that ASC significantly (e.g., 78.3% higher throughput) outperforms a state-of-the-art generative inference framework (i.e., FlexGen) that implements KVC across various model sizes, input and output sequence lengths, and GPUs.

关键词： Tensors Costs Translation Computational modeling Memory management Graphics processing units Performance gain Throughput parallel architectures Computational complexity

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Retargeting Applications for Heterogeneous Systems with the Tribble Source-to-Source Framework 32

Retargeting Applications for Heterogeneous Systems with the ...

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32nd International conference on parallel architectures and compilation techniques (PACT)

作者： Sousa, Luis Miguel Bispo, Joao Paulino, Nuno Univ Porto Porto Portugal INESC TEC Porto Portugal

ISBN: (纸本)9798350342543

Advancements in semiconductor technology no longer occur at the pace the industry had been accustomed to. We have entered what is considered by many to be the post-Moore era. In order to continue scaling performance, increasingly heterogeneous architectures are being developed and the use of special purpose accelerators is on the rise. One notable example are Field-Programmable-Gate-Arrays (FPGAs), both in the data-center and embedded spaces. Advances in FPGA features and tools is allowing for critical kernels to be accelerated on specialized hardware without fabrication costs. However, re-targeting code to such heterogeneous platforms still requires significant refactoring of the compute intensive kernels, as well as knowledge of parallel compute and hardware design concepts for maximization of performance. We present Tribble, a source-to-source framework under active development, capable of transforming regular C/C++ programs for execution on heterogeneous architectures. This includes transforming the target kernel source code so that it is amenable for circuit generation while keeping the original version for software execution, inserting code for task and memory management and injecting a scheduler algorithm.

关键词： Source-to-Source Heterogeneous architectures Hardware-Software Partitioning Co-design

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QeiHaN: An Energy-Efficient DNN Accelerator that Leverages Log Quantization in NDP architectures 32

QeiHaN: An Energy-Efficient DNN Accelerator that Leverages L...

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32nd International conference on parallel architectures and compilation techniques (PACT)

作者： Khabbazan, Bahareh Riera, Marc Gonzalez, Antonio Univ Politecn Catalunya UPC Barcelona Spain

ISBN: (纸本)9798350342543

The constant growth of DNNs makes them challenging to implement and run efficiently on traditional compute-centric architectures. Some works have attempted to enhance accelerators by adding more compute units and on-chip buffers, but they often worsen the memory issue due to increased bandwidth demands. Memory-centric designs based on Near-Data Processing (NDP) have been proposed to mitigate this problem by moving computations closer to the memory hierarchy. Leveraging 3D-stacked memory for its storage density and nearmemory processing capabilities, this paper introduces QeiHaN, a hardware accelerator that optimizes DNN inference efficiency. QeiHaN employs a 3D-stacked memory-centric weight storage scheme combined with a logarithmic quantization of activations, resulting in reduced memory accesses by 25%. Evaluation demonstrates significant speedup and energy savings compared to a Neurocube-like accelerator across various DNNs.

关键词： DNN NDP Quantization Exponential

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Automatic Algorithm-Based Fault Tolerance (AABFT) of Stencil Computations 32

Automatic Algorithm-Based Fault Tolerance (AABFT) of Stencil...

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32nd International conference on parallel architectures and compilation techniques (PACT)

作者： Narmour, Louis Derrien, Steven Rajopadhye, Sanjay Univ Rennes Inria CNRS IRISA Rennes France Colorado State Univ Ft Collins CO 80523 USA

ISBN: (纸本)9798350342543

In this work, we study fault tolerance of transient errors, such as those occurring due to cosmic radiation or hardware component aging and degradation, using Algorithm-Based Fault Tolerance (ABFT). ABFT methods typically work by adding some additional computation in the form of invariant checksums which, by definition, should not change as the program executes. By computing and monitoring checksums, it is possible to detect errors by observing differences in the checksum values. However, this is challenging for two key reasons: (1) it requires careful manual analysis of the input program, and (2) care must be taken to subsequently carry out the checksum computations efficiently enough for it to be worth it. Prior work has shown how to apply ABFT schemes with low overhead for a variety of input programs. Here, we focus on a subclass of programs called stencil applications, an important class of computations found widely in various scientific computing domains. We propose a new compilation scheme to automatically analyze and generate the checksum computations. To the best of our knowledge, this is the first work to do such a thing in a compiler. We show that low overhead code can be easily generated and provide a preliminary evaluation of the tradeoff between performance and effectiveness.

关键词： fault-tolerance program transformations polyhedral compilation stencils

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Accelerating Decision-Tree-based Inference through Adaptive parallelization 32

Accelerating Decision-Tree-based Inference through Adaptive ...

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32nd International conference on parallel architectures and compilation techniques (PACT)

作者： van Lunteren, Jan IBM Res Europe Ruschlikon Switzerland

ISBN: (纸本)9798350342543

Gradient-boosted trees and random forests are among the most popular machine learning algorithms. They are applied to a broad spectrum of applications as diverse as search engine ranking, credit card fraud detection, customer relationship management, fault diagnosis in machinery, and geological studies, to name a few. Inference of these models is supported by many widely-used libraries and frameworks including Scikit-Learn, XGBoost, and ONNX Runtime. Many of the inference algorithms integrated in these libraries are optimized for performing fast predictions for large input batches, often targeted at ensemble models containing relatively shallow decision trees. This does not necessarily match well with the requirements of new emerging applications that depend on real-time predictions for individual samples or small input batches. Also, cloud-based inference services put more emphasis on small memory footprints. This paper aims to fill this gap by proposing a novel inference scheme for decision-tree ensembles that efficiently handles a wider range of application requirements and model characteristics. Performance is maximized for an extensive number of parameter combinations through a new concept in which a predict function is selected dynamically at runtime. This is done in a way that the processing resources, including the use of SIMD vector processing units and multithreading, are optimally exploited. Experiments have shown substantial performance improvements over state-of-the-art algorithms for common models.

关键词： decision trees random forests machine learning parallel processing multithreading

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A CPU-FPGA Holistic Source-To-Source compilation Approach for Partitioning and Optimizing C/C plus plus Applications 32

A CPU-FPGA Holistic Source-To-Source Compilation Approach fo...

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32nd International conference on parallel architectures and compilation techniques (PACT)

作者： Santos, Tiago Bispo, Joao Cardoso, Joao M. P. Univ Porto FEUP Porto Portugal Univ Porto INESC TEC Porto Portugal

ISBN: (纸本)9798350342543

A common approach for improving performance uses FPGAs to accelerate critical code regions, which often involves two processes: hardware/software partitioning, which identifies regions to offload to the FPGA;and optimizing those regions (e.g., through HLS directives). As both processes are separate and usually applied in sequence, the interplay between them is unnatural, and it is unclear how the choices made in one step can benefit the choices made in the other step. This paper presents our work-in-progress for combining partitioning and optimization into a single holistic process. First, our source-to-source compiler builds a task-based representation from the input application. Then, a greedy algorithm builds clusters of tasks and assigns each cluster to either hardware (FPGA) or software (CPU). The algorithm iteratively refines the clusters and offloading decisions by: a) minimizing the communication costs between clusters by assigning tasks that work with shared data to the same cluster;b) reducing the global execution time by applying code optimizations to the tasks in each cluster. We show the impact of our holistic approach to a motivating edge detection example and compare the results when applying partitioning and code optimizations as independent steps. The results show that a holistic partitioning can lead to a speedup of up to 28.7x when compared to a simple offloading of the application to an FPGA.

关键词： Source-to-Source Compiler Hardware/Software Partitioning High-level Synthesis FPGA

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An Architecture for Resilient Federated Learning Through parallel Recognition 31

An Architecture for Resilient Federated Learning Through Par...

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31st International conference on parallel architectures and compilation techniques (PACT)

作者： Kim, Jeongeun Jeong, Youngwoo Jang, Suyeon Lee, Seung Eun Seoul Natl Univ Sci & Technol Seoul South Korea

ISBN: (纸本)9781450398688

In federated learning, non-independent and identically distributed (non-IID) local datasets lead to accuracy loss compared to homogeneous distribution of datasets. In this paper, we propose an architecture for improving accuracy and offering resilience through federation utilizing non-IID datasets. The proposed architecture performs parallel recognition employing triplication of AI processors with different intelligence. Experimental results demonstrate that the proposed architecture improves accuracy by 2.3% compared to accuracy of a single AI processor on average and guarantees resilience.

关键词： Architecture

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UPIR: Toward the Design of Unified parallel Intermediate Representation for parallel Programming Models 31

UPIR: Toward the Design of Unified Parallel Intermediate Rep...

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31st International conference on parallel architectures and compilation techniques (PACT)

作者： Wang, Anjia Yi, Xinyao Yan, Yonghong Univ North Carolina Charlotte Charlotte NC 28223 USA

ISBN: (纸本)9781450398688

The complexity of heterogeneous computing architectures, as well as the demand for productive and portable parallel application development, have driven the evolution of parallel programming models to become more comprehensive and complex than before. Enhancing the conventional compilation technologies and software infrastructure to be parallelism-aware has become one of the main goals of recent compiler development. In this work, we propose the design of unified parallel intermediate representation (UPIR) for multiple parallel programming models and for enabling unified compiler transformation for the models. UPIR specifies three commonly used parallelism patterns (SPMD, data and task parallelism), data attributes and explicit data movement and memory management, and synchronization operations used in parallel programming. We demonstrate UPIR via a prototype implementation in the ROSE compiler for unifying IR for both OpenMP and OpenACC and in both C/C++ and Fortran, for unifying the transformation that lowers both OpenMP and OpenACC code to LLVM runtime, and for exporting UPIR to LLVM MLIR dialect. The fully extended paper of this abstract can be found from https://***/abs/2209.10643.

关键词： Compiler transformation parallel intermediate representation OpenMP OpenACC MLIR

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