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检索条件"任意字段=Proceedings of the Conference on Parallel Architectures and Compilation Techniques"

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Maximizing System Utilization via parallelism Management for Co-Located parallel Applications 18

Maximizing System Utilization via Parallelism Management for...

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27th IEEE/ACM/IFIP International conference on parallel architectures and compilation techniques (PACT)

作者： Cho, Younghyun Guzman, Camilo A. Celis Egger, Bernhard Seoul Natl Univ Seoul South Korea

ISBN: (纸本)9781450359863

With an increasing number of cores and memory controllers in multiprocessor platforms, co-location of parallel applications is gaining on importance. Key to achieve good performance is allocating the proper number of threads to co-located applications. This paper presents NuPoCo, a framework for automatically managing parallelism of co-located parallel applications on NUMA multi-socket multi-core systems. NuPoCo maximizes the utilization of CPU cores and memory controllers by dynamically adjusting the number of threads for co-located parallel applications. Evaluated with various scenarios of co-located OpenMP applications on a 64-core AMD and a 72-core Intel machine, NuPoCo achieves a reduction of the total turnaround time by 10-20% compared to the default Linux scheduler and an existing parallelism management policy focusing on CPU utilization only.

关键词： parallelism management resource utilization OpenMP

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MEMODYN: Exploiting Weakly Consistent Data Structures for Dynamic parallel Memoization 18

MEMODYN: Exploiting Weakly Consistent Data Structures for Dy...

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27th IEEE/ACM/IFIP International conference on parallel architectures and compilation techniques (PACT)

作者： Prabhu, Prakash Beard, Stephen R. Apostolakis, Sotiris Zaks, Ayal August, David I. Google India Bengaluru Karnataka India Princeton Univ Princeton NJ 08544 USA Intel Corp Haifa Israel

ISBN: (纸本)9781450359863

Several classes of algorithms for combinatorial search and optimization problems employ memoization data structures to speed up their serial convergence. However, accesses to these data structures impose dependences that obstruct program parallelization. Such programs often continue to function correctly even when queries into these data structures return a partial view of their contents. Weakening the consistency of these data structures can unleash new parallelism opportunities, potentially at the cost of additional computation. These opportunities must, therefore, be carefully exploited for overall speedup. This paper presents MEMODYN, a framework for parallelizing loops that access data structures with weakly consistent semantics. MEMODYN provides programming abstractions to express weak semantics, and consists of a parallelizing compiler and a runtime system that automatically and adaptively exploit the semantics for optimized parallel execution. Evaluation of MEMODYN shows that it achieves efficient parallelization, providing significant improvements over competing techniques in terms of both runtime performance and solution quality.

关键词： Implicit parallelism programming model weakly consistent data structures automatic parallelization memoization runtime adaptivity tuning

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GATE: A Generalized Dataflow-level Approximation Tuning Engine For Data parallel architectures 19

GATE: A Generalized Dataflow-level Approximation Tuning Engi...

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56th ACM/EDAC/IEEE Design Automation conference (DAC)

作者： Kang, Seokwon Yu, Yongseung Kim, Jiho Park, Yongjun Hanyang Univ Dept Comp Sci Seoul South Korea Korea Adv Inst Sci & Techinol Sch Elect Engn Daejon South Korea

ISBN: (纸本)9781450367257

Although approximate computing is widely used, it requires substantial programming effort to find appropriate approximation patterns among multiple pre-defined patterns to achieve a high performance. Therefore, we propose an automatic approximation framework called GATE to uncover hidden opportunities from any data-parallel program regardless of the code pattern or application characteristics using two compiler techniques, namely subgraph-level approximation (SGLA) and approximate thread merge (ATM). GATE also features conservative/aggressive tuning and dynamic calibration to maximize the performance while maintaining the TOQ level during runtime. Our framework achieves an average performance gain of 2.54x over the baseline with minimum accuracy

关键词： Logic gates Runtime Performance gain Kernel Tuning Approximate computing

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MetaPerturb: transferable regularizer for heterogeneous tasks and architectures 20

MetaPerturb: transferable regularizer for heterogeneous task...

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proceedings of the 34th International conference on Neural Information Processing Systems

作者： Jeongun Ryu Jaewoong Shin Hae Beom Lee Sung Ju Hwang KAIST KAIST and AITRICS South Korea

ISBN: (纸本)9781713829546

Regularization and transfer learning are two popular techniques to enhance model generalization on unseen data, which is a fundamental problem of machine learning. Regularization techniques are versatile, as they are task- and architecture-agnostic, but they do not exploit a large amount of data available. Transfer learning methods learn to transfer knowledge from one domain to another, but may not generalize across tasks and architectures, and may introduce new training cost for adapting to the target task. To bridge the gap between the two, we propose a transferable perturbation, MetaPerturb, which is meta-learned to improve generalization performance on unseen data. MetaPerturb is implemented as a set-based lightweight network that is agnostic to the size and the order of the input, which is shared across the layers. Then, we propose a meta-learning framework, to jointly train the perturbation function over heterogeneous tasks in parallel. As MetaPerturb is a set-function trained over diverse distributions across layers and tasks, it can generalize to heterogeneous tasks and architectures. We validate the efficacy and generality of MetaPerturb trained on a specific source domain and architecture, by applying it to the training of diverse neural architectures on heterogeneous target datasets against various regularizers and fine-tuning. The results show that the networks trained with MetaPerturb significantly outperform the baselines on most of the tasks and architectures, with a negligible increase in the parameter size and no hyperparameters to tune.

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On-The-FlyWorkload Partitioning for Integrated CPU/GPU architectures 18

On-The-FlyWorkload Partitioning for Integrated CPU/GPU Archi...

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27th IEEE/ACM/IFIP International conference on parallel architectures and compilation techniques (PACT)

作者： Cho, Younghyun Negele, Florian Park, Seohong Egger, Bernhard Gross, Thomas R. Seoul Natl Univ Seoul South Korea Swiss Fed Inst Technol Zurich Switzerland

ISBN: (纸本)9781450359863

Integrating CPUs and GPUs on the same die provides new opportunities for optimization, especially for irregular data-parallel workloads that fail to fully exploit the computational power of the GPU. Such workloads benefit from a proper partitioning between the CPU and the GPU. This paper presents an on-the-fly workload partitioning technique for irregular workloads on integrated architectures. Unlike existing work, no prior analysis of the workload is required. GPU kernels and input data are analyzed and optimized at runtime. The technique executes work chunks of similar load on the GPU and assigns irregular chunks to the CPU. Evaluated with various irregular workloads, the method achieves a 1.4x-7.1x speedup over GPU execution on AMD and Intel processors.

关键词： Integrated architecture workload partitioning OpenCL

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16th IFIP WG 12.5 International conference on Artificial Intelligence Applications and Innovations, AIAI 2020

16th IFIP WG 12.5 International Conference on Artificial Int...

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16th IFIP WG 12.5 International conference on Artificial Intelligence Applications and Innovations, AIAI 2020

ISBN: (纸本)9783030491604

The proceedings contain 75 papers. The special focus in this conference is on Artificial Intelligence Applications and Innovations. The topics include: Manifold learning for innovation funding: Identification of potential funding recipients;network aggregation to enhance results derived from multiple analytics;PolicyCLOUD: Analytics as a service facilitating efficient data-driven public policy management;demand forecasting of short life cycle products using data mining techniques;Arbitrary scale super-resolution for brain MRI images;knowledge-based fusion for image tampering localization;Transfer learning using convolutional neural network architectures for brain tumor classification from MRI images;a novel learning automata-based strategy to generate melodies from chordal inputs;graph neural networks to advance anticancer drug design;Boosted ensemble learning for anomaly detection in 5G RAN;optimizing self-organizing lists-on-lists using transitivity and pursuit-enhanced object partitioning;task-projected hyperdimensional computing for multi-task learning;cross-domain authorship attribution using pre-trained language models;indoor localization with multi-objective selection of Radiomap models;STDP plasticity in TRN within hierarchical spike timing model of visual information processing;Tensor-based CUDA optimization for ANN inferencing using parallel acceleration on embedded GPU;the random neural network in price predictions;joint multi-object detection and segmentation from an untrimmed video;robust 3D detection in traffic scenario with tracking-based coupling system;Automated MeSH indexing of biomedical literature using contextualized word representations;machine learning for cognitive load classification – A case study on contact-free approach;knowledge-based management and reasoning on cultural and natural touristic routes;ontological foundations of modelling security policies for logical analytics;RDF reasoning on large ontologies: A study on cultural heritage

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CPpf : a prefetch aware LLC partitioning approach 19

CPpf : a prefetch aware LLC partitioning approach

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48th International conference on parallel Processing (ICPP)

作者： Xiao, Jun Pimentel, Andy D. Liu, Xu Univ Amsterdam Amsterdam Netherlands Coll William & Mary Williamsburg VA 23187 USA

ISBN: (纸本)9781450362955

Hardware cache prefetching is deployed in modern multicore processors to reduce memory latencies, addressing the memory wall problem. However, it tends to increase the Last Level Cache (LLC) contention among applications in multiprogrammed workloads, leading to a performance degradation for the overall system. To study the interaction between hardware prefetching and LLC cache management, we first analyze the variation of application performance when varying the effective LLC space in the presence and absence of hardware prefetching. We observe that hardware prefetching can compensate the application performance loss due to the reduced effective cache space. Motivated by this observation, we classify applications into two categories, prefetching sensitive (PS) and non prefetching sensitive (NPS) applications, by the degree of performance benefit they experience from hardware prefetchers. To address the cache contention and also to mitigate the potential prefetch-related cache interference, we propose CPpf, a cache partitioning approach for improving the shared cache management in the presence of hardware prefetching. CPpf consists of a method using Precise Event-Based Sampling techniques for the online classification of PS and NPS applications and a cache partitioning scheme using Cache Allocation technology to distribute the cache space among PS and NPS applications. We implemented CPpf as a user-level runtime system on Linux. Compared with a non-partitioning approach, CPpf achieves speedups of up to 1.20, 1.08 and 1.06 for workloads with 2, 4 and 8 single-threaded applications, respectively. Moreover, it achieves speedups of up to 1.22 and 1.11 for workloads composed of two applications with 4 threads and 8 threads, respectively.

关键词： Cache partitioning Hardware prefetching Multi-core architectures Shared cache Cache allocation technology

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GraphPhi: Efficient parallel Graph Processing on Emerging Throughput-oriented architectures 18

GraphPhi: Efficient Parallel Graph Processing on Emerging Th...

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27th IEEE/ACM/IFIP International conference on parallel architectures and compilation techniques (PACT)

作者： Peng, Zhen Powell, Alexander Wu, Bo Bicer, Tekin Ren, Bin Coll William & Mary Williamsburg VA 23185 USA Colorado Sch Mines Golden CO 80401 USA Argonne Natl Lab Lemont IL USA

ISBN: (纸本)9781450359863

Modern parallel architecture design has increasingly turned to throughput-oriented devices to address concerns about energy efficiency and power consumption. However, graph applications cannot tap into the full potential of such architectures because of highly unstructured computations and irregular memory accesses. In this paper, we present GraphPhi, a new approach to graph processing on emerging Intel Xeon Phi-like architectures, by addressing the restrictions of migrating existing graph processing frameworks on shared-memory multi-core CPUs to this new architecture. Specifically, GraphPhi consists of 1) an optimized hierarchically blocked graph representation to enhance the data locality for both edges and vertices within and among threads, 2) a hybrid vertex-centric and edge-centric execution to efficiently find and process active edges, and 3) a uniform MIMD-SIMD scheduler integrated with a lock-free update support to achieve both good thread-level load balance and SIMD-level utilization. Besides, our efficient MIMD-SIMD execution is capable of hiding memory latency by increasing the number of concurrent memory access requests, thus benefiting more from the latest High-Bandwidth Memory technique. We evaluate our GraphPhi on six graph processing applications. Compared to two state-of-the-art shared-memory graph processing frameworks, it results in speedups up to 4X and 35X, respectively.

关键词： Graph Processing Xeon Phi MIMD-SIMD Execution

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Massively parallel Skyline Computation For Processing-In-Memory architectures 18

Massively Parallel Skyline Computation For Processing-In-Mem...

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27th IEEE/ACM/IFIP International conference on parallel architectures and compilation techniques (PACT)

作者： Zois, Vasileios Gupta, Divya Tsotras, Vassilis J. Najjar, Walid A. Roy, Jean-Francois Univ Calif Riverside Riverside CA 92521 USA UPMEM SAS Grenoble France

ISBN: (纸本)9781450359863

Processing-In-Memory (PIM) is an increasingly popular architecture aimed at addressing the 'memory wall' crisis by prioritizing the integration of processors within DRAM. It promotes low data access latency, high bandwidth, massive parallelism, and low power consumption. The skyline operator is a known primitive used to identify those multi-dimensional points offering optimal trade-offs within a given dataset. For large multidimensional dataset, calculating the skyline is extensively compute and data intensive. Although, PIM systems present opportunities to mitigate this cost, their execution model relies on all processors operating in isolation with minimal data exchange. This prohibits direct application of known skyline optimizations which are inherently sequential, creating dependencies and large intermediate results that limit the maximum parallelism, throughput, and require an expensive merging phase. In this work, we address these challenges by introducing the first skyline algorithm for PIM architectures, called DSky. It is designed to be massively parallel and throughput efficient by leveraging a novel work assignment strategy that emphasizes load balancing. Our experiments demonstrate that it outperforms the state-of-the-art algorithms for CPUs and GPUs, in most cases. DSky achieves 2x to 14x higher throughput compared to the state-of-the-art solutions on competing CPU and GPU architectures. Furthermore, we showcase DSky's good scaling properties which are intertwined with PIM's ability to allocate resources with minimal added cost. In addition, we showcase an order of magnitude better energy consumption compared to CPUs and GPUs.

关键词： processing-in-memory skyline queries pareto dominance massive parallelism processing-near-memory load balancing

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An Efficient Graph Accelerator with parallel Data Conflict Management 18

An Efficient Graph Accelerator with Parallel Data Conflict M...

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27th IEEE/ACM/IFIP International conference on parallel architectures and compilation techniques (PACT)

作者： Yao, Pengcheng Zheng, Long Liao, Xiaofei Jin, Hai He, Bingsheng Huazhong Univ Sci & Technol Big Data Technol & Syst Lab Cluster & Grid Comp Lab Serv Comp Technol & Syst Lab Wuhan 430074 Hubei Peoples R China Natl Univ Singapore Sch Comp Singapore 117418 Singapore

ISBN: (纸本)9781450359863

Graph-specific computing with the support of dedicated accelerator has greatly boosted the graph processing in both efficiency and energy. Nevertheless, their data conflict management is still sequential when certain vertex needs a large number of conflicting updates at the same time, leading to prohibitive performance degradation. This is particularly true and serious for processing natural graphs. In this paper, we have the insight that the atomic operations for the vertex updating of many graph algorithms (e.g., BFS, PageRank, and WCC) are typically incremental and simplex. This hence allows us to parallelize the conflicting vertex updates in an accumulative manner. We architect AccuGraph, a novel graph-specific accelerator that can simultaneously process atomic vertex updates for massive parallelism while ensuring the correctness. A parallel accumulator is designed to remove the serialization in atomic protections for conflicting vertex updates through merging their results in parallel. Our implementation on Xilinx FPGA with a wide variety of typical graph algorithms shows that our accelerator achieves an average throughput by 2.36 GTEPS as well as up to 3.14x performance speedup in comparison with state-of-the-art ForeGraph (with its single-chip version).

关键词： Atoms

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