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Technology-Aware Logic Synthesis for ReRAM based In-Memory Computing

Technology-Aware Logic Synthesis for ReRAM based In-Memory C...

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Design, Automation and Test in Europe conference and Exhibition (DATE)

作者： Bhattacharjee, Debjyoti Amaru, Luca Chattopadhyay, Anupam Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore Synopsys Mountain View CA USA

ISBN: (纸本)9783981926309

Resistive RAMs (ReRAMs) have gained prominence for design of logic-in-memory circuits and architectures due to fast read/write speeds, high endurance, density and logic operation capabilities. ReRAM crossbar arrays allow constrained bit-level parallel operations. In this paper, for the first time, we propose optimization techniques during logic synthesis, which are specifically targeted for leveraging the parallelism offered by ReRAM crossbar arrays. Our method uses Majority-Inverter Graph (MIG) for the internal representation of the Boolean functions. The novel optimization techniques, when applied to the MIG, exposes the hit-level parallelism, and is further coupled with an efficient technology mapping flow. The entire synthesis process is benchmarked exhaustively over large arithmetic functions using a representative ReRAM crossbar architecture, while varying the crossbar dimensions. For the hard benchmarks, we obtained 10% reduction in the number of nodes with 16% reduction in delay on average.

关键词： Optimization Computer architecture Boolean functions parallel processing Resistive RAM Logic arrays

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JUST-IN-TIME parallel SIMULATION 18

JUST-IN-TIME PARALLEL SIMULATION

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Winter Simulation conference (WSC)

作者： Hannon, Christopher Jin, Dong Santhi, Nandakishore Eidenbenz, Stephan Liu, Jason IIT Dept Comp Sci Chicago IL 60616 USA Los Alamos Natl Lab Informat Sci CCS 3 Los Alamos NM 87545 USA Florida Int Univ Sch Comp & Informat Sci Miami FL 33199 USA

ISBN: (纸本)9781538665725

Due to the evolution of programming languages, interpreted languages have gained widespread use in scientific and research computing. Interpreted languages excel at being portable, easy to use, and fast in prototyping than their ahead-of-time (AOT) counterparts, including C,C++, and Fortran. While traditionally considered as slow to execute, advancements in Just-in-Time (JIT) compilation techniques have significantly improved the execution speed of interpreted languages and in some cases outperformed AOT languages. In this paper, we explore some challenges and design strategies in developing a high performance parallel discrete event simulation engine, called Simian, written with interpreted languages with JIT capabilities, including Python, Lua, and Javascript. Our results show that Simian with JIT performs similarly to AOT simulators, such as MiniSSF and ROSS. We expect that with features like good performance, user-friendliness, and portability, the just-in-time parallel simulation will become a common choice for modeling and simulation in the near future.

关键词： Engines Synchronization Python Computational modeling Runtime Optimization Tools

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In-Memory Data Flow Processor 26

In-Memory Data Flow Processor

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26th International conference on parallel architectures and compilation techniques (PACT)

作者： Fujiki, Daichi Mahlke, Scott Das, Reetuparna Univ Michigan Ann Arbor MI 48109 USA

ISBN: (纸本)9781509067640

The efficiency of the proposed in-memory processor comes from two sources. First, massive parallelism. Non-volatile memories (NVMs) are composed of several thousands of arrays. Each of these arrays are transformed into ALUs which can compute concurrently. Second, reduction in data movement, by avoiding shuffling of data between memory and processor cores. Our goal is to establish the programming semantics and execution models to expose the above benefits of ReRAM computing to general purpose data parallel programs. This poster we will present a programming framework, compiler, ISA, and architecture of our proposed general purpose in-memory data flow processor built out of resistive compute memories. We will also present our experimental results across micro-benchmarks and real-world benchmarks from PARSEC and Rodinia. Initial results demonstrate 800x and 100x speedup when compared to multi-core and GPU execution.

关键词： Nonvolatile memory parallel processing Programming Memory architecture Arrays Space exploration

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Run-time Requirement Enforcement for Loop Programs on Processor Arrays 18

Run-time Requirement Enforcement for Loop Programs on Proces...

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16th ACM/IEEE International conference on Formal Methods and Models for System Design (MEMOCODE)

作者： Witterauf, Michael Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci Hardware Software Codesign Erlangen Germany

ISBN: (纸本)9781538661956

Loop bounds are often unknown until run time, making it difficult to analyze non-functional properties such as latency at compile-time. Similarly, static allocations of processing resources to loop computations might be too conservative with respect to given performance requirements, or not optimal with respect to the energy consumption. To still satisfy requirements when accelerating loop nests under this uncertainty of loop bounds, we formalize and propose an approach to run-time requirement enforcement: at run time, select a mapping among a set of candidates that satisfies a given set of requirements while optimizing secondary objectives. Because the candidate search space of suitable mappings might be prohibitively large to evaluate at run time, we further introduce two approaches to reduce its cardinality: 1) architecture-specific reduction by solving for parts of the mapping from the requirements, and 2) design-time reduction by finding a k-subset of mappings that maximizes the number of loop bounds where the requirements are satisfied. We implemented our proposed run-time requirement enforcement techniques for a representative class of programmable processor array architecture called tightly coupled processor arrays (TCPAs) and demonstrate their effectiveness with a case study. The case study shows the effectiveness of our approach: We can satisfy given latency requirements while easily saving up to 10% in energy.

关键词： embedded systems Linux multiprocessing systems parallel processing power aware computing program compilers program control structures reconfigurable architectures power aware computing program control structures Runtime Loops compilers Multiprocessing systems Reconfigurable architectures Contraceptive Coil Linux parallel PROCESSING (COMPUTERS) Embedded systems MAPPING(MATHEMATICAL) ARRAY PROCESSORS enforcement

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proceedings of PMBS 2018: Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems, Held in conjunction with SC 2018: The International conference for High Performance Computing, Networking, Storage and Analysis

Proceedings of PMBS 2018: Performance Modeling, Benchmarking...

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2018 IEEE/ACM Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems, PMBS 2018

ISBN: (纸本)9781728101828

The proceedings contain 13 papers. The topics discussed include: a metric for evaluating supercomputer performance in the era of extreme heterogeneity;evaluating SLURM simulator with real-machine SLURM and vice versa;automated instruction stream throughput prediction for Intel and AMD microarchitectures;deep learning at scale on NVIDIA V100 accelerators;algorithm selection of MPI collectives using machine learning techniques;miniVite: a graph analytics benchmarking tool for massively parallel systems;and improving MPI reduction performance for manycore architectures with OpenMP and data compression.

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Performance Improvement via Always-Abort HTM 26

Performance Improvement via Always-Abort HTM

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26th International conference on parallel architectures and compilation techniques (PACT)

作者： Izraelevitz, Joseph Xiang, Lingxiang Scott, Michael L. Univ Rochester Dept Comp Sci Rochester NY 14627 USA Intel Corp Parallel Comp Lab Santa Clara CA USA

ISBN: (纸本)9781509067640

Several research groups have noted that hardware transactional memory (HTM), even in the case of aborts, can have the side effect of warming up the branch predictor and caches, thereby accelerating subsequent execution. We propose to employ this side effect deliberately, in cases where execution must wait for action in another thread. In doing so, we allow "warm-up" transactions to observe inconsistent state. We must therefore ensure that they never accidentally commit. To that end, we propose that the hardware allow the program to specify, at the start of a transaction, that it should in all cases abort, even if it (accidentally) executes a commit instruction. We discuss several scenarios in which always-abort HTM (AAHTM) can be useful, and present lock and barrier implementations that employ it. We demonstrate the value of these implementations on several real-world applications, obtaining performance improvements of up to 2.5x with almost no programmer effort.

关键词： hardware transactional memory thread-level speculation locks barriers

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An Efficient parallel Algorithm for Mining Both Frequent Closed and Generator Sequences on Multi-core Processors 5

An Efficient Parallel Algorithm for Mining Both Frequent Clo...

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5th NAFOSTED conference on Information and Computer Science (NICS)

作者： Hai Duong Tin Truong Bac Le Univ Dalat Dept Math & Comp Sci Da Lat Vietnam VNU HCM Univ Nat Sci Dept Comp Sci Ho Chi Minh Vietnam

ISBN: (纸本)9781538679838

Compared to frequent sequence mining that is a computationally challenging task with many intermediate subsequences, frequent closed and generator sequence mining provides several benefits because it results in increased efficiency and concise representations while preserving all the information of all traditional patterns recovered from the representations. Besides, frequent closed sequences can be combined with generators to generate non-redundant sequential rules and to recover all sequential patterns as well as their frequencies quickly. However, most algorithms that have been proposed to discover either closed sequences or generators at a time and for large databases containing many long sequences are still too long to complete the work or run out of memory. Therefore, this paper, by exploiting the advantage of multi-core processor architectures, proposes a novel parallel algorithm called Par-GenCloSM for simultaneously mining both frequent closed and generator sequences in the same process. Par-GenCloSM is based on efficient techniques to quickly eliminate unpromising candidate branches and two novel strategies named EPUCloGen and GPPCloGen to reduce the global synchronization cost of the parallel model and speed up the mining process. ParGenCloSM is the first parallel algorithm for mining frequent closed sequences and generators concurrently. Experimental results on many real-life and synthetic databases show that Par-GenCloSM outperforms state-of-the-art algorithms in terms of runtime and memory consumption, especially for long sequence databases with low minimum support thresholds.

关键词： Sequential pattern mining frequent closed sequence frequent generator sequence multi-core processors parallel mining

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A Generalized Framework for Automatic Scripting Language parallelization 26

A Generalized Framework for Automatic Scripting Language Par...

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26th International conference on parallel architectures and compilation techniques (PACT)

作者： Oh, Taewook Beard, Stephen R. Johnson, Nick P. Popovych, Sergiy August, David I. Princeton Univ Princeton NJ 08544 USA Facebook Menlo Pk CA 94025 USA DE Shaw Res New York NY USA

ISBN: (纸本)9781509067640

Computational scientists are typically not expert programmers, and thus work in easy to use dynamic languages. However, they have very high performance requirements, due to their large datasets and experimental setups. Thus, the performance required for computational science must be extracted from dynamic languages in a manner that is transparent to the programmer. Current approaches to optimize and parallelize dynamic languages, such as just-in-time compilation and highly optimized interpreters, require a huge amount of implementation effort and are typically only effective for a single language. However, scientists in different fields use different languages, depending upon their needs. This paper presents techniques to enable automatic extraction of parallelism within scripts that are universally applicable across multiple different dynamic scripting languages. The key insight is that combining a script with its interpreter, through program specialization techniques, will embed any parallelism within the script into the combined program that can then be extracted via automatic parallelization techniques. Additionally, this paper presents several enhancements to existing speculative automatic parallelization techniques to handle the dependence patterns created by the specialization process. A prototype of the proposed technique, called Partial Evaluation with parallelization (PEP), is evaluated against two open-source script interpreters with 6 input linear algebra kernel scripts each. The resulting geomean speedup of 5.10x on a 24-core machine shows the potential of the generalized approach in automatic extraction of parallelism in dynamic scripting languages.

关键词： Multicore Processing parallel processing

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PACT 2014 - proceedings of the 23rd International conference on parallel architectures and compilation techniques

PACT 2014 - Proceedings of the 23rd International Conference...

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23rd International conference on parallel architectures and compilation techniques, PACT 2014

ISBN: (纸本)9781450328098

The proceedings contain 53 papers. The topics discussed include: virtues and limitations of commodity hardware transactional memory;tiling and optimizing time-iterated computations over periodic domains;ATCache: reducing DRAM cache latency via a small SRAM tag cache;SpongeDirectory: flexible sparse directories utilizing multi-level memristors;EFetch: optimizing instruction fetch for event-driven web applications;Xstream: cross-core spatial streaming based MLC prefetchers for parallel applications in CMPS;warp-aware trace scheduling for GPUs;Invyswell: a hybrid transactional memory for Haswell's restricted transactional memory;consolidated conflict detection for hardware transactional memory;Velociraptor: an embedded compiler toolkit for numerical programs targeting CPUs and GPUs;memory scheduling towards high-throughput cooperative heterogeneous computing;PEMOGEN: automatic adaptive performance modeling during program runtime;and VAST: the illusion of a large memory space for GPUs.

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Automated accelerator generation and optimization with composable, parallel and pipeline architecture 18

Automated accelerator generation and optimization with compo...

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55th Annual Design Automation conference, DAC 2018

作者： Cong, Jason Wei, Peng Yu, Cody Hao Zhang, Peng University of California Los Angeles United States Falcon Computing Solutions Inc. United States

ISBN: (纸本)9781450357005

CPU-FPGA heterogeneous architectures feature flexible acceleration of many workloads to advance computational capabilities and energy efficiency in today's datacenters. This advantage, however, is often overshadowed by the poor programmability of FPGAs. Although recent advances in high-level synthesis (HLS) significantly improve the FPGA programmability, it still leaves programmers facing the challenge of identifying the optimal design configuration in a tremendous design space. In this paper we propose the composable, parallel and pipeline (CPP) microarchitecture as an accelerator design template to substantially reduce the design space. Also, by introducing the CPP analytical model to capture the performanceresource trade-offs, we achieve efficient, analytical-based design space exploration. Furthermore, we develop the AutoAccel framework to automate the entire accelerator generation process. Our experiments show that the AutoAccel-generated accelerators outperform their corresponding software implementations by an average of 72x for a broad class of computation kernels. © 2018 Association for Computing Machinery.

关键词： Field programmable gate arrays (FPGA)

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