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Constant-Based Truncated Cubing architectures 60

Constant-Based Truncated Cubing Architectures

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60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Bui, Son Stine, James E. Oklahoma State Univ VLSI Comp Architecture Res Grp Elect & Comp Engn Dept Stillwater OK 74078 USA

ISBN: (纸本)9781509063895

A new technique for computing the truncated cube of an operand at length of power two is proposed, implemented, analyzed, and compared to existing techniques. The new proposed method is comparable to previously proposed methods that compute the cube of an operand in parallel. Post layout results are presented in a 65nm Application Specific Integrated Circuit implementation and are compared against previous methods. Results demonstrate an area reduction compared to previous cubing architectures and considerable energy reduction using truncated cubing architectures.

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Generalized micro-specialization for modern DBMS architectures

Generalized micro-specialization for modern DBMS architectur...

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2017 ACM International conference on Management of Data, SIGMOD 2017

作者： He, Wei Department of Computer Science University of Arizona United States

ISBN: (纸本)9781450341998

Performance considerations are crucial for DBMSes and have led to numerous innovations in DBMS architecture in recent years, including columnar stores, the operator-ata-time execution model, and query compilation. However, there are some sources of runtime overhead that these techniques do not address. Micro-specialization uses information about runtime invariants in DBMS code to dynamically specialize frequently executed code snippets, thereby optimizing away overheads arising from the generic nature of the original DBMS code. However, micro-specialization as originally presented suffers from some shortcomings that limit its applicability. It is limited in the kinds of invariants that it considers and its application to modern architectural features, such as operator-at-a-time model and query compilation, can be problematic. Furthermore, some of the overheads that are eliminated in the original work on micro-specialization of PostgreSQL are also optimized away in columnar store architectures, thereby raising the question of whether the approach can yield comparably significant performance improvements on modern DBMS architectures. Our research generalizes micro-specialization to address these shortcomings. The principal contributions are as follows. First, we introduce the notion of a class of generalized invariants, that enables a much wider variety of optimizations, including many that would not be possible in the original formulation of micro-specialization. Second, we extend traditional micro-specialization to deal with key characteristics of modern DBMS architectures, namely, columnar-store, operator-at-a-time model, and query compilation. Third, we show that the resulting approach of generalized microspecialization is able to obtain significant performance increases on a modern DBMS architecture that are already highly optimized through these three extant approaches. © 2017 Copyright held by the owner/author(s).

关键词： Database systems

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CPU/GPU Collaboration techniques for Transfer Learning on Mobile Devices. 23

CPU/GPU Collaboration Techniques for Transfer Learning on Mo...

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23rd IEEE International conference on parallel and Distributed Systems (ICPADS)

作者： Valery, Olivier Liu, Pangfeng Wu, Jan-Jan Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei Taiwan Natl Taiwan Univ Grad Inst Networking & Multimedia Dept Comp Sci & Informat Engn Taipei Taiwan Acad Sinica Inst Informat Sci Res Ctr Informat Technol Innovat Taipei Taiwan

ISBN: (纸本)9781538621295

As mobile devices become more capable, the need for customization of mobile services becomes increasingly important for users. Nowadays, mobile device sensors are able to collect information from users throughout the day, which gives insight into their profiles. The advent of modern System-on-Chip architectures has enabled mobile devices to tackle machine learning-oriented problems heretofore reserved to desktop computers. The recent success of deep learning makes it a method of choice for understanding the complex user patterns on mobile devices. Unfortunately, training a deep neural network is often considered as too computationally intensive on mobile devices. To address this issue, we consider transfer learning, a technique that aims to take advantage of deep learning features that have been previously learned to improve the learning performance of another neural network. In this paper, we propose a deep learning framework TransferCL, that supports transfer learning on mobile devices. Our approach relies on the collaboration of the multicore CPU and the integrated GPU to accelerate deep learning computation on mobile devices. We consider three major issues - performance/portability tradeoff, power efficiency, and memory management, propose our approaches, and conduct experiments to evaluate them.

关键词： OpenCL GPGPU mobile computing heterogeneous system System-on-Chip deep learning transfer learning

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ACM International conference Proceeding Series

ACM International Conference Proceeding Series

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8th Workshop on parallel Programming and Run-Time Management techniques for Many-Core architectures and 6th Workshop on Design Tools and architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2017

ISBN: (纸本)9781450348775

The proceedings contain 6 papers. The topics discussed include: dataflow acceleration of Scikit-learn Gaussian process regression;VectorPU: a generic and efficient data-container and component model for transparent data transfer on GPU-based heterogeneous systems;using PEGs for automatic extraction of memory access descriptions to support data-parallel pattern recognition;on boosting energy-efficiency of heterogeneous embedded systems via game theory;scaling binarized neural networks on reconfigurable logic;MTP-Caffe: memory, timing, and power aware tool for mapping CNNs to GPUs.

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32nd International conference on High Performance Computing, ISC High Performance 2017

32nd International Conference on High Performance Computing,...

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32nd International conference on High Performance Computing, ISC High Performance 2017

ISBN: (纸本)9783319676296

The proceedings contain 53 papers. The special focus in this conference is on High Performance Computing. The topics include: Simulation of hierarchical storage systems for TCO and QoS;gPU erasure coding for campaign storage;pIOM-PX: A framework for modeling the I/O behavior of parallel scientific applications;real-time I/O-monitoring of hpc applications with SIOX, elasticsearch, grafana and FUSE;output performance study on a production petascale filesystem;gPU-accelerated particle-in-cell code on minsky;pushing big data into accelerators: Can the JVM saturate our hardware?;the technological roadmap of parallware and its alignment with the OpenPOWER ecosystem;on the scalability of data reduction techniques in current and upcoming HPC systems from an application perspective;experiences evaluating functionality and performance of IBM POWER8+ systems;power/performance controlling techniques in OpenPOWER;performance evaluation of container-based high performance computing ecosystem using OpenPOWER;pre-exascale architectures: OpenPOWER performance and usability assessment for french scientific community;iXPUG: Experiences on intel knights landing at the one year mark;analyzing performance of selected NESAP applications on the cori HPC system;on the mitigation of cache hostile memory access patterns on many-core CPU architectures;from knights corner to landing: A case study based on a hodgkin-huxley neuron simulator;porting tissue-scale cardiac simulations to the knights landing platform;kART – A runtime compilation library for improving HPC application performance;toward a multi-method approach: Lossy data compression for climate simulation data;performance evaluation of nwchem ab-initio molecular dynamics (AIMD) simulations on the intel® xeon phi™ processor;performance variability on xeon phi;scaling the EOS namespace.

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Comparative Analysis of parallel OPIR Compression on Space Processors

Comparative Analysis of Parallel OPIR Compression on Space P...

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IEEE Aerospace conference

作者： Ho, An Shea, Eric George, Alan Gordon-Ross, Ann Univ Florida ECE Dept NSF Ctr High Performance Reconfigurable Comp CHRE Room 327Larsen Hall Gainesville FL 32611 USA Univ Pittsburgh ECE Dept NSF Ctr High Performance Reconfigurable Comp CHRE Room 1238DBenedum Hall Pittsburgh PA 15261 USA

ISBN: (纸本)9781509016136

Requirements for higher video quality in space applications continuously calls for increased resolution in imaging sensors, higher bit-depth codecs, more creative solutions for preprocessing and compression techniques, and faster, yet resilient, space-grade platforms. Understanding how these variables interact and affect each other on different platforms is crucial in system development when trying to meet requirements and constraints, such as compression speed, compression ratio (CR), image quality, bandwidth, etc. To analyze this interaction, we present a comparative analysis between compression speed and compression ratio using serial and parallel compression codes on different platforms and architectures, focusing upon video data from overhead-persistent infrared (OPIR) sensors on spacecraft. Previous research allowed us to compare CR and image quality with new preprocessing techniques, but it did not evaluate and address the challenges of compression speed on space-grade processors. Performance is critical, since of course the preprocessing and compression codes plus downlink of compressed data must require less total time than downlink of the raw data, in order for compression to be fully effective.

关键词： Transportation Supply and demand Programming Linear programming Approximation algorithms Resource management

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Exploring the parallel implementations of the three classical MST algorithms

Exploring the parallel implementations of the three classica...

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International conference on Inventive Communication and Computational Technologies (ICICCT)

作者： Latha, N. R. Shyamala, G. Prasad, G. R. BMS Coll Engn Dept Comp Sci & Engn Bangalore Karnataka India

ISBN: (纸本)9781509052974

Minimum spanning tree (MST) is one among the most studied combinatorial problems with practical applications in VLSI layout and routing, wireless communication and distributed networks, current problems in biology and medicine such as cancer detection, medical imaging, and proteomics, and national security and bioterrorism[1]. Since Minimum Spanning Tree (MST) is one of the well-known classical graph problems it finds its application in various fields and many attempts are being done to improve the speed of MST using parallel computing. Most of the previous attempts made were either too complicated to implement or they perform well only on special graphs with regular structure. The widespread adaption of multicore platforms and GPU's has offered the opportunity to explore new implementation techniques for many algorithms that were originally designed for uniprocessors. By formulating new parallel schemes, the programmers would be able to exploit the multiple hardware frameworks offered in today's platforms in a more efficient way. A category of problems among the most challenging to parallelize are the ones that exhibit inherently sequential characteristics. The discovery of the Single Source Shortest Path or the composition of the Minimum Spanning Forest of a given graph falls into this category. This paper is a survey on the different parallel MST algorithms that are implemented on Multicore architectures.

关键词： parallel Minimum spanning tree algorithm Bor(o)uvka's algorithm Kruskal's algorithm Prim's algorithm

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Architectural Review of Polynomial Bases Finite Field Multipliers Over GF(2m)

Architectural Review of Polynomial Bases Finite Field Multip...

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International conference on Communication, Computing and Digital Systems (C-CODE)

作者： Imran, Malik Rashid, Muhammad Abasyn Univ Elect Engn Dept Islamabad Pakistan Umm Al Qura Univ Comp Engn Dept Mecca Saudi Arabia

ISBN: (纸本)9781509044481

In elliptic curve cryptography (ECC), hardware architectures of finite field (FF) multipliers are frequently proposed for polynomial as well as for normal bases representations over GF(2m). Although the polynomial bases provide efficient FF multiplication as compared to normal bases, the performance of the entire elliptic cryptosystem mainly depends upon its FF multiplier. Consequently, this paper provides a comparative overview of the recent hardware architectures of FF multipliers for polynomial bases over GF(2m). This is achieved by classifying the most recent state-of-the-art research practices into three categories: bit-serial, bitparallel and digit-serial multipliers. The comparison of multiple techniques in this article enables the designer to select a suitable multiplier according to different application requirements such as high speed/performance, constrained environments and high throughput/area applications.

关键词： polynomial bases finite field multipliers hardware architectures bit-serial bit-parallel digit serial

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POSTER: An Optimization of Dataflow architectures for Scientific Applications 16

POSTER: An Optimization of Dataflow Architectures for Scient...

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International conference on parallel architectures and compilation (PACT)

作者： Shen, Xiaowei Ye, Xiaochun Tan, Xu Wang, Da Zhang, Zhimin Fan, Dongrui Tang, Zhimin Chinese Acad Sci Inst Comp Technol SKL Comp Architecture Beijing 100864 Peoples R China Univ Chinese Acad Sci Beijing Peoples R China

ISBN: (纸本)9781450341219

Dataflow computing is proved to be promising in high-performance computing. However, traditional dataflow architectures are general-purpose and not efficient enough when dealing with typical scientific applications due to low utilization of function units. In this paper, we propose an optimization of dataflow architectures for scientific applications. The optimization introduces a request for operands mechanism and a topology based instruction mapping algorithm to improve the efficiency of dataflow architectures. Experimental results show that the request for operands optimization achieves a 4.6% average performance improvement over the traditional dataflow architectures and the TBIM algorithm achieves a 2.28x and a 1.98x average performance improvement over SPDI and SPS algorithm respectively.

关键词： Request for operands topology-based instruction mapping dataflow computing high-performance computing

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A resource-efficient monitoring architecture for hardware accelerated self-adaptive online data stream compression 21

A resource-efficient monitoring architecture for hardware ac...

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21st IEEE Signal Processing: Algorithms, architectures, Arrangements, and Applications, SPA 2017

作者： Najmabadi, Seyyed Mahdi Pandit, Prajwala Tran, Trung-Hieu Simon, Sven Department of Parallel Systems University of Stuttgart Stuttgart70569 Germany

ISBN: (纸本)9788362065301

In this paper, a novel scalable and resource-efficient architecture capable of monitoring the compressibility of a data stream with various entropy encoding algorithms is proposed. The self-adaptive architecture determines the best compression technique among many techniques which may be selected to encode an online data stream. This information can be used to reconfigure an adaptive encoding architecture dynamically at runtime to provide a high compression ratio. We have compared two hardware architectures that model the same functionality but perform the processing of the input data differently. This paper contributes a resource-efficient self-adaptive way of selecting the best lossless data compression method in hardware, independent of the end application. The processing architecture which uses soft-core processors provides approximately 35% resource savings as compared to the hardware implementation of processing modules in VHDL. Our experimental results show that the overall compression achieved by using self-adaptive architectures is around 14% better than that provided by the best compression technique in a non-adaptive system. © 2017 Division of Signal Processing and Electronic Systems, Poznan University of Technology.

关键词： Signal encoding

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