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检索条件"任意字段=Proceedings of the Conference on Parallel Architectures and Compilation Techniques"

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Massively parallel Open Modification Spectral Library Searching with Hyperdimensional Computing 31

Massively Parallel Open Modification Spectral Library Search...

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31st International conference on parallel architectures and compilation techniques (PACT)

作者： Kang, Jaeyoung Xu, Weihong Bittremieux, Wout Rosing, Tajana Univ Calif San Diego La Jolla CA 92093 USA

ISBN: (纸本)9781450398688

Mass spectrometry, for protein identification, generates a massive number of spectra that need to be matched against a large database. In reality, most spectra remain mismatched due to unexpected post-translational modifications. Open modification search (OMS) improves the identification rate by considering every possible change in spectra, but it expands the search space exponentially. We propose HyperOMS, which redesigns OMS based on hyperdimensional computing to cope with such challenges. HyperOMS encodes floating-point spectral data with high-dimensional binary vectors, enabling the massive parallelism in OMS. Experimental results show that HyperOMS on GPU is up to 17x faster and 6.4x more energy efficient than the state-of-the-art GPU-based OMS tool [2] while providing comparable search quality.

关键词： Mass spectrometry

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compilation On The GPU? A Feasibility Study 22

Compilation On The GPU? A Feasibility Study

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19th ACM International conference on Computing Frontiers (CF)

作者： Voetter, Robin F. Huijben, Marcel Rietveld, Kristian F. D. Leiden Univ LIACS Leiden Netherlands

ISBN: (纸本)9781450393386

The emergence of highly parallel architectures has led to a renewed interest in parallel compilation. In particular, the widespread availability of GPU architectures raises the question whether compilation on the GPU is feasible. In this paper, we describe the first design and implementation of a parallel compiler from a simple imperative programming language to RISC-V machine code, that is fully executed on a GPU. To accomplish this, all stages from parsing to machine code generation were redesigned to exploit fine-grained parallelism. Experimental evaluation of the implemented prototype demonstrates our proposed parallel techniques to be effective and implementation of compilation on the GPU to be feasible. Finally, we propose a number of avenues for future work and hope to revitalize research into parallel compilation conducted in the 1980s.

关键词： parallel compilation GPUs Compiler Construction Parsing Code Generation

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GPU Adaptive In-situ parallel Analytics (GAP) 31

GPU Adaptive In-situ Parallel Analytics (GAP)

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31st International conference on parallel architectures and compilation techniques (PACT)

作者： Xing, Haoyuan Agrawal, Gagan Ramnath, Rajiv Ohio State Univ Columbus OH 43210 USA Augusta Univ Augusta GA USA

ISBN: (纸本)9781450398688

Despite the popularity of in-situ analytics in scientifc computing, there is only limited work to date on in-situ analytics for simulations running on GPUs. Notably, two unaddressed challenges are 1) performing memory-efcient in-situ analysis on accelerators and 2)automatically choosing the processing resources and suitable data representation for a given query and platform. This paper addresses both problems. First, GAP makes several new contributions toward making bitmap indices suitable, effective, and efcient as a compressed data summary structure for the GPUs this includes introducing a layout structure, a method for generating multi-attribute bitmaps, and novel techniques for bitmap-based processing of major operators that comprise complex data analytics. Second, this paper presents a performance modeling methodology, aiming to predict the placement (i.e., CPU or GPU) and the data representation choice (summarization or original) that yield the best performance on a given confguration. Our extensive evaluation of complex in-situ queries and real-world simulations shows that with our methods, analytics on GPU using bitmaps almost always outperforms other options, and the GAP performance model predicts the optimal placement and data representation for most scenarios. © 2022 Association for Computing Machinery.

关键词： Graphics processing unit

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Optimization of parallel compilation techniques using genetic algorithms

Optimization of parallel compilation techniques using geneti...

引用

2024 International conference on Computer Network Security and Software Engineering, CNSSE 2024

作者： Han, Lin Yan, Pengyan Zhengzhou University Henan Zhengzhou450001 China National Super Computing Center in Zhengzhou Henan Zhengzhou450001 China

ISBN: (纸本)9781510680234

This paper addresses the issue of low parallel efficiency resulting from fixed thread allocation in automatic parallelization compilation technology. The authors employ a genetic algorithm to determine the optimal number of threads for individual parallelizable loops. They then utilize iterative compilation techniques to produce the suitable number of threads for each parallelizable loop structure, thereby enhancing the efficiency of automatic parallelization compilation. The proposed method demonstrated an average performance enhancement of 26% across 10 benchmarks in the SPEC CPU2006 test suite and an overall performance improvement of 3.7% in the NPB3.4.2 test suite, thereby indicating the viability and efficacy of the approach. The approach outlined in this paper can be utilized as a benchmark for enhancing the effectiveness of automated parallel computing and promoting the progression of automated parallel computing technology. © 2024 SPIE.

关键词： Genetic algorithms

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HBMax: Optimizing Memory Efficiency for parallel Influence Maximization on Multicore architectures 31

HBMax: Optimizing Memory Efficiency for Parallel Influence M...

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31st International conference on parallel architectures and compilation techniques (PACT)

作者： Chen, Xinyu Minutoli, Marco Tian, Jiannan Halappanavar, Mahantesh Kalyanaraman, Ananth Tao, Dingwen Washington State Univ Pullman WA USA Pacif Northwest Natl Lab Richland WA USA Indiana Univ Bloomington IN 47405 USA

ISBN: (纸本)9781450398688

Influence maximization aims to select k most-influential vertices or seeds in a network, where influence is defined by a given diffusion process. Although computing optimal seed set is NP-Hard, efficient approximation algorithms exist. However, even state-of-the-art parallel implementations are limited by a sampling step that incurs large memory footprints. This in turn limits the problem size reach and approximation quality. In this work, we study the memory footprint of the sampling process collecting reverse reachability information in the IMM (Influence Maximization via Martingales) algorithm over large real-world social networks. We present a memory-efficient optimization approach (called HBMax) based on Ripples, a state-of-the-art multi-threaded parallel influence maximization solution. Our approach, HBMax, uses a portion of the reverse reachable (RR) sets collected by the algorithm to learn the characteristics of the graph. Then, it compresses the intermediate reverse reachability information with Huffman coding or bitmap coding, and queries on the partially decoded data, or directly on the compressed data to preserve the memory savings obtained through compression. Considering a NUMA architecture, we scale up our solution on 64 CPU cores and reduce the memory footprint by up to 82.1% with average 6.3% speedup (encoding overhead is offset by performance gain from memory reduction) without loss of accuracy. For the largest tested graph Twitter7 (with 1.4 billion edges), HBMax achieves 5.9x compression ratio and 2.2x speedup.

关键词： Influence maximization compression multicore architectures

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Revolutionizing compilation: Lexical Analysis Approaches for parallel Multi-Core Processing 7

Revolutionizing Compilation: Lexical Analysis Approaches for...

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7th International conference on Inventive Computation Technologies, ICICT 2024

作者： Vaikunta Pai, T. Sandeep Kumar, S. Nethravathi, P.S. Department of Ise Nitte India Department of Cce Nitte India Shree Devi Institute of Technology Department of Cse Mangalore India

ISBN: (数字)9798350359299

ISBN: (纸本)9798350359299

Lexical analysis is a crucial phase in compiler design that involves transforming a stream of characters into meaningful tokens. Traditional lexical analyzers utilize finite automata and regular expressions to achieve this task. However, in the context of modern computing environments such as multi-core machines, there is a growing need to enhance the efficiency of this process. Exploring the concept of parallel tokenization and its application in lexical analysis to harness the power of multi-core architectures, the research delves into innovative approaches for optimizing compilation processes. By leveraging the processing capabilities of multi-core machines, the scanning process can be significantly expedited. Exploring the challenges, benefits, and implementation considerations of parallel tokenization, the research investigates the potential to revolutionize the field of compiler design through the parallel processing of tokens. The study undertakes a methodical review of relevant literature, thereby addressing emerging strategies and concerns surrounding lexical analyzer implementation, as well as the adoption of enhanced methodologies. The outcomes of this review showcase an array of techniques, recent advancements, and contemporary approaches concerning the deployment of both auto-generated and hand-crafted scanners. Grounded in these findings, the paper extrapolates insights into the effectiveness of lexical analyzer implementation strategies, consequently charting out potential research challenges and unexplored domains necessitating investigation in the realm of implementation of lexical analysis processes. © 2024 IEEE.

关键词： parallel architectures

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parallelizing Neural Network Models Effectively on GPU by Implementing Reductions Atomically 31

Parallelizing Neural Network Models Effectively on GPU by Im...

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31st International conference on parallel architectures and compilation techniques (PACT)

作者： Zhao, Jie Bastoul, Cedric Yi, Yanzhi Hu, Jiahui Nie, Wang Zhang, Renwei Geng, Zhen Li, Chong Tachon, Thibaut Gan, Zhiliang State Key Lab Math Engn & Adv Comp Zhengzhou Zhengzhou Peoples R China Huawei Technol France SASU Paris France Huawei Technol Co Ltd Beijing Peoples R China

ISBN: (纸本)9781450398688

Due to the missing of a good orchestration of loop transformations, existing optimizing compilers for deploying neural networks on GPU either parallelize reductions ineffectively or miss the fusion opportunities with other operators. Neural network models thus exhibit sub-optimal performance on GPU. We present a practical approach called Panamera for the effective parallelization of reductions in neural networks on GPU. Panamera first leverages loop coalescing to flatten the loop dimensions of reductions, converting all reduction operators into canonical forms eligible for the polyhedral model. Next, Panamera uses polyhedral transformations to reduce the data movements caused by unfused reductions and perform multi-block hardware binding not considered by many compilers. Finally, Panamera embeds a highly optimized routine implemented using GPU atomic instructions, further improving the performance of neural network models while guaranteeing the correctness of parallel reductions. The experimental results demonstrate the effectiveness of our approach: for single operators our code obtains a mean speedup of 33.7x, 3.5x, 5.4x and 9.6x over cuDNN, CUB, TVM and Ansor, for sub-graphs our approach outperforms cuDNN, TVM and Ansor by 9.5x, 2.6x and 2.7x, and for end-to-end workloads, a tensor compiler integrated with our approach outperforms them by 122.5%, 19.3% and 15.2%.

关键词： deep learning reduction GPU polyhedral compilation

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Auto-Partitioning Heterogeneous Task-parallel Programs with StreamBlocks 31

Auto-Partitioning Heterogeneous Task-Parallel Programs with ...

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31st International conference on parallel architectures and compilation techniques (PACT)

作者： Emami, Mahyar Bezati, Endri Janneck, Jorn W. Larus, James R. Ecole Polytech Fed Lausanne Lausanne Switzerland Huawei Technol Comp Syst Lab Zurich Switzerland Lund Univ Lund Sweden

ISBN: (纸本)9781450398688

FPGAs play an increasing role in the reconfigurable accelerator landscape. A key challenge in designing FPGA-based systems is partitioning computation between processor cores and FPGAs. An appropriate division of labor is difficult to predict in advance and requires experiments and measurements. When an investigation requires rewriting part of the system in a new language or with a new programming model, its high cost can delay design-space exploration. A single-language system with an appropriate programming model and compiler that targets both platforms transforms this tedious exploration to a simple recompile with new compiler directives. This work introduces StreamBlocks, a unified open-source software/FPGA compiler and runtime that takes dataflow programs written in Cal, and automatically partitions them across heterogeneous CPU/FPGA platforms. The explicit task-parallel semantics of dataflow allows our compiler to simultaneously take advantage of thread parallelism on software and spatial parallelism on hardware. StreamBlocks is augmented with a profile-guided autopartitioning tool that helps identify the best hardware-software partitions. We demonstrate the capability of our compiler in finding the right balance between hardware and software execution on both a high-end datacenter accelerator card and an embedded board. Our experiments exhibit a 4 - 7x speedup over trivial partitions. This speedup is achieved automatically with zero code modifications.

关键词： reconfigurable computing Actors partitioning

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Custom High-Performance Vector Code Generation for Data-Specific Sparse Computations 31

Custom High-Performance Vector Code Generation for Data-Spec...

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31st International conference on parallel architectures and compilation techniques (PACT)

作者： Horro, Marcos Pouchet, Louis-Noel Rodriguez, Gabriel Tourino, Juan Univ A Coruna CITIC La Coruna Spain Colorado State Univ Ft Collins CO USA

ISBN: (纸本)9781450398688

Sparse computations, such as sparse matrix-dense vector multiplication, are notoriously hard to optimize due to their irregularity and memory-boundedness. Solutions to improve the performance of sparse computations have been proposed, ranging from hardware-based such as gather-scatter instructions, to software ones such as generalized and dedicated sparse formats, used together with specialized executor programs for different hardware targets. These sparse computations are often performed on read-only sparse structures: while the data themselves are variable, the sparsity structure itself does not change. Indeed, sparse formats such as CSR have a typically high cost to insert/remove nonzero elements in the representation. The typical use case is to not modify the sparsity during possibly repeated computations on the same sparse structure. In this work, we exploit the possibility to generate a specialized executor program dedicated to the particular sparsity structure of an input matrix. It creates opportunities to remove indirection arrays and synthesize regular, vectorizable code for such computations. But, at the same time, it introduces challenges in code size and instruction generation, as well as efficient SIMD vectorization. We present novel techniques and extensive experimental results to efficiently generate SIMD vector code for data-specific sparse computations, and study the limits in terms of applicability and performance of our techniques compared to state-of-practice highperformance libraries like Intel MKL.

关键词： vectorization data-specific compilation sparse data structure

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Efficient task-mapping of parallel applications using a space-filling curve 31

Efficient task-mapping of parallel applications using a spac...

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31st International conference on parallel architectures and compilation techniques (PACT)

作者： Kwon, Oh-Kyoung Kang, Ji-Hoon Lee, Seungchul Kim, Wonjung Song, Junehwa Korea Adv Inst Sci & Technol Daejeon South Korea Korea Inst Sci & Technol Informat Daejeon South Korea

ISBN: (纸本)9781450398688

Improving the communication performance of parallel programs is an important but difficult problem in a large-scale distributed memory-based cluster. Efforts to improve parallel scalability often face severe huddles in managing communication overheads. This paper proposes a framework of a space-filing curve(SFC)-based task-remapping for communication intensive parallel applications. An SFC-based mapping, when applied for task-mapping of parallel applications preserves locality in terms of communications and produce a less fragmented task-mapping, reducing communication overheads. The framework also provides tools for performance analysis to see if the proposed task-mapping is appropriate for a given application running on a target system. It further develops a binary classifier as a predictor to decide whether or not to apply the proposed mapping before run-time. We evaluate the framework with three communication intensive applications in Cartesian coordinates: P3DFFT solver and Channel code using 2D domain decomposition model, and Poisson solver using 3D domain decomposition. The evaluation is conducted on a large-scale cluster system of fat-tree topology with up to 1,024 compute nodes. The proposed task-mapping achieves the overall performance improvement ranging from similar to 30% to similar to 66% over the baseline approach depending on the workloads. Also, when used in combination with the binary classifier-based predictor, it achieves the expected performance gains from 4% to 8%.

关键词： Mapping

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