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检索条件"任意字段=Proceedings of the Conference on Parallel Architectures and Compilation Techniques"

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Enabling Pipeline parallelism in Heterogeneous Managed Runtime Environments via Batch Processing 2022

Enabling Pipeline Parallelism in Heterogeneous Managed Runti...

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18th ACM SIGPLAN/SIGOPS International conference on Virtual Execution Environments (VEE)

作者： Blanaru, Florin Stratikopoulos, Athanasios Fumero, Juan Kotselidis, Christos Univ Manchester Manchester Lancs England

ISBN: (纸本)9781450392518

During the last decade, managed runtime systems have been constantly evolving to become capable of exploiting underlying hardware accelerators, such as GPUs and FPGAs. Regardless of the programming language and their corresponding runtime systems, the majority of the work has been focusing on the compiler front trying to tackle the challenging task of how to enable just-in-time compilation and execution of arbitrary code segments on various accelerators. Besides this challenging task, another important aspect that defines both functional correctness and performance of managed runtime systems is that of automatic memory management. Although automatic memory management improves productivity by abstracting away memory allocation and maintenance, it hinders the capability of using specific memory regions, such as pinned memory, in order to perform data transfer times between the CPU and hardware accelerators. In this paper, we introduce and evaluate a series of memory optimizations specifically tailored for heterogeneous managed runtime systems. In particular, we propose: (i) transparent and automatic "parallel batch processing" for overlapping data transfers and computation between the host and hardware accelerators in order to enable pipeline parallelism, and (ii) "off-heap pinned memory" in combination with parallel batch processing in order to increase the performance of data transfers without posing any on-heap overheads. These two techniques have been implemented in the context of the state-of-the-art open-source TornadoVM and their combination can lead up to 2.5x end-to-end performance speedup against sequential batch processing.

关键词： Data Transfers GPUs Heterogeneous architectures Memory Management Optimizations Virtual Machines

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Improving performance of SYCL applications on CPU architectures using LLVM-directed compilation flow 13

Improving performance of SYCL applications on CPU architectu...

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13th International Workshop on Programming Models and Applications for Multicores and Manycores (PMAM) part of PPoPP conference

作者： Ghiglio, Pietro Dolinsky, Uwe Goli, Mehdi Narasimhan, Kumudha Codeplay Software Ltd Edinburgh Scotland

ISBN: (纸本)9781450393393

The wide adoption of SYCL as an open-standard API for accelerating C++ software in domains such as HPC, Automotive, Artificial Intelligence, Machine Learning, and other areas necessitates efficient compiler and runtime support for a growing number of different platforms. Existing SYCL implementations provide support for various devices like CPUs, GPUs, DSPs, FPGAs, etc, typically via OpenCL or CUDA backends. While accelerators have increased the performance of user applications significantly, employing CPU devices for further performance improvement is beneficial due to the significant presence of CPUs in existing datacenters. SYCL applications on CPUs, currently go through an OpenCL backend. Though an OpenCL backend is valuable in supporting accelerators, it may introduce additional overhead for CPUs since the host and device are the same. Overheads like a run-time compilation of the kernel, transferring of input/output memory to/from the OpenCL device, invoking the OpenCL kernel, may not be necessary when running on the CPU. While some of these overheads (such as data transfer) can be avoided by modifying the application, it can introduce disparity in the SYCL application's ability to achieve performance portability on other devices. In this paper, we propose an alternate approach to running SYCL applications on CPUs. We bypass OpenCL and use a CPU-directed compilation flow, along with the integration of Whole Function Vectorization to generate optimized host and device code together in the same translation unit. We compare the performance of our approach - the CPU-directed compilation flow, with an OpenCL backend for existing SYCL-based applications, with no code modification. We run experiments across various CPU architectures to attest to the efficacy of our proposed approach.

关键词： SYCL parallel programming multi-cores software acceleration portability standards compiler optimizations

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Neuroevolution of Recurrent architectures on Control Tasks 22

Neuroevolution of Recurrent Architectures on Control Tasks

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Genetic and Evolutionary Computation conference (GECCO)

作者： Le Clei, Maximilien Bellec, Pierre Univ Montreal Geriatr Inst Montreal PQ Canada

ISBN: (纸本)9781450392686

Modern artificial intelligence works typically train the parameters of fixed-sized deep neural networks using gradient-based optimization techniques. Simple evolutionary algorithms have recently been shown to also be capable of optimizing deep neural network parameters, at times matching the performance of gradient-based techniques, e.g. in reinforcement learning settings. In addition to optimizing network parameters, many evolutionary computation techniques are also capable of progressively constructing network architectures. However, constructing network architectures from elementary evolution rules has not yet been shown to scale to modern reinforcement learning benchmarks. In this paper we therefore propose a new approach in which the architectures of recurrent neural networks dynamically evolve according to a small set of mutation rules. We implement a massively parallel evolutionary algorithm and run experiments on all 19 OpenAI Gym state-based reinforcement learning control tasks. We find that in the majority of cases, dynamic agents match or exceed the performance of gradient-based agents while utilizing orders of magnitude fewer parameters. We believe our work to open avenues for real-life applications where network compactness and autonomous design are of critical importance. We provide our source code, final model checkpoints and full results at ***/MaximilienLC/nra.

关键词： Network architecture

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A CPU-FPGA Holistic Source-To-Source compilation Approach for Partitioning and Optimizing C/C++ Applications

A CPU-FPGA Holistic Source-To-Source Compilation Approach fo...

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International conference on parallel Architecture and compilation techniques (PACT)

作者： Tiago Santos João Bispo João M.P. Cardoso Univ. of Porto FEUP and INESC-TEC Porto Portugal

A common approach for improving performance uses FPGAs to accelerate critical code regions, which often involves two processes: hardware/software partitioning, which identifies regions to offload to the FPGA; and optimizing those regions (e.g., through HLS directives). As both processes are separate and usually applied in sequence, the interplay between them is unnatural, and it is unclear how the choices made in one step can benefit the choices made in the other step. This paper presents our work-in-progress for combining partitioning and optimization into a single holistic process. First, our source-to-source compiler builds a task-based representation from the input application. Then, a greedy algorithm builds clusters of tasks and assigns each cluster to either hardware (FPGA) or software (CPU). The algorithm iteratively refines the clusters and offloading decisions by: a) minimizing the communication costs between clusters by assigning tasks that work with shared data to the same cluster; b) reducing the global execution time by applying code optimizations to the tasks in each cluster. We show the impact of our holistic approach to a motivating edge detection example and compare the results when applying partitioning and code optimizations as independent steps. The results show that a holistic partitioning can lead to a speedup of up to $28.7\times$ when compared to a simple offloading of the application to an FPGA.

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PathSeeker: A Fast Mapping Algorithm for CGRAs

PathSeeker: A Fast Mapping Algorithm for CGRAs

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25th Design, Automation and Test in Europe conference and Exhibition (DATE)

作者： Balasubramanian, Mahesh Shrivastava, Aviral Arizona State Univ Make Programming Simple Lab Tempe AZ 85281 USA

ISBN: (纸本)9783981926361

Coarse-grained reconfigurable arrays (CGRAs) have gained traction over the years as a low-power accelerator due to the efficient mapping of the compute-intensive loops onto the 2-D array by the CGRA compiler. When encountering a mapping failure for a given node, existing mapping techniques either exit and retry the mapping anew, or perform backtracking, i.e., recursively remove the previously mapped node to find a valid mapping. Abandoning mapping and starting afresh can deteriorate the quality of mapping and the compilation time. Even backtracking may not be the best choice since the previous node may not be the incorrectly placed node. To tackle this issue, we propose PathSeeker - a mapping approach that analyzes mapping failures and performs local adjustments to the schedule to obtain a mapping. Experimental results on 35 top performance-critical loops from MiBench, Rodinia, and Parboil benchmark suites demonstrate that PathSeeker can map all of them with better mapping quality and dramatically less compilation time than the previous state-of-the-art approaches - GraphMinor and RAMP, which were unable to map 20 and 5 loops, respectively. Over these benchmarks, PathSeeker achieves 28% better performance at 550x compilation speedup over GraphMinor and 3% better performance at 10x compilation speedup over RAMP on a 4x4 CGRA.

关键词： Compilers Reconfigurable architectures CGRA Mapping

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Exploiting Multi-Level Task Dependencies to Prune Redundant Work in Relax-Ordered Task-parallel Algorithms 19

Exploiting Multi-Level Task Dependencies to Prune Redundant ...

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proceedings of the International conference on parallel architectures and compilation techniques

作者： Masab Ahmad Mohsin Shan Akif Rehman Omer Khan University of Connecticut Storrs CT USA

ISBN: (纸本)9781728136134

Work-efficient task-parallel algorithms enforce ordering between tasks using queuing primitives. Such algorithms offer limited parallelism due to queuing constraints that result in data movement and synchronization bottlenecks. Speculatively relaxing order of tasks across cores using the Galois framework shows promise as false dependencies generated by strict queuing constraints are mitigated to unlock task parallelism. However, relaxed ordering results in redundant work, for which Galois relies on static measures to improve work-efficiency. This paper proposes a dynamic multi-level parent-child task dependency checking mechanism in Galois to prune redundant work by exploiting monotonic properties of shared data values. Evaluation on a 40-core Intel Xeon multicore shows an average of 2× performance improvements over state-of-the-art ordered and relax ordered graph algorithms.

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QeiHaN: An Energy-Efficient DNN Accelerator that Leverages Log Quantization in NDP architectures 23

QeiHaN: An Energy-Efficient DNN Accelerator that Leverages L...

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proceedings of the 32nd International conference on parallel architectures and compilation techniques

作者： Bahareh Khabbazan Marc Riera Antonio González Universitat Politècnica de Catalunya (UPC) Barcelona Spain

ISBN: (纸本)9798350342543

The constant growth of DNNs makes them challenging to implement and run efficiently on traditional compute-centric architectures. Some works have attempted to enhance accelerators by adding more compute units and on-chip buffers, but they often worsen the memory issue due to increased bandwidth demands. Memory-centric designs based on Near-Data Processing (NDP) have been proposed to mitigate this problem by moving computations closer to the memory hierarchy. Leveraging 3D-stacked memory for its storage density and near-memory processing capabilities, this paper introduces QeiHaN, a hardware accelerator that optimizes DNN inference efficiency. QeiHaN employs a 3D-stacked memory-centric weight storage scheme combined with a logarithmic quantization of activations, resulting in reduced memory accesses by 25%. Evaluation demonstrates significant speedup and energy savings compared to a Neurocube-like accelerator across various DNNs.

关键词： DNN

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OSDP: Optimal Sharded Data parallel for Distributed Deep Learning 32

OSDP: Optimal Sharded Data Parallel for Distributed Deep Lea...

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32nd International Joint conference on Artificial Intelligence (IJCAI)

作者： Jiang, Youhe Fu, Fangcheng Miao, Xupeng Nie, Xiaonan Cui, Bin Peking Univ Sch CS Beijing Peoples R China Peking Univ Key Lab High Confidence Software Technol MOE Beijing Peoples R China Carnegie Mellon Univ Comp Sci Dept Pittsburgh PA USA Peking Univ Qingdao Inst Computat Social Sci Qingdao Peoples R China

ISBN: (纸本)9781956792034

Large-scale deep learning models contribute to significant performance improvements on varieties of downstream tasks. Current data and model parallelism approaches utilize model replication and partition techniques to support the distributed training of ultra-large models. However, directly deploying these systems often leads to sub-optimal training efficiency due to the complex model architectures and the strict device memory constraints. In this paper, we propose Optimal Sharded Data parallel (OSDP), an automated parallel training system that combines the advantages from both data and model parallelism. Given the model description and the device information, OSDP makes trade-offs between the memory consumption and the hardware utilization, thus automatically generates the distributed computation graph and maximizes the overall system throughput. In addition, OSDP introduces operator splitting to further alleviate peak memory footprints during training with negligible overheads, which enables the trainability of larger models as well as the higher throughput. Extensive experimental results of OSDP on multiple different kinds of large-scale models demonstrate that the proposed strategy outperforms the state-of-the-art in multiple regards.

关键词： Personnel training

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A Classification of Malware Sandboxes and Their architectures

A Classification of Malware Sandboxes and Their Architecture...

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2025 Joint National conference on Cybersecurity, ITASEC and SERICS 2025

作者： Bistarelli, Stefano Burberi, Emanuele P. Santini, Francesco Dipartimento di Matematica e Informatica Università degli Studi di Perugia Perugia Italy

The development of sandboxes has evolved in parallel with malware improvements, providing secure environments for the execution and analysis of malicious software. With the increasing number of sandboxes being developed, each offering distinct features, selecting the most suitable solution for specific needs has become increasingly complex. This paper aims to thoroughly understand sandbox technologies by introducing their foundational concepts and offering a detailed review of currently available solutions. We categorize sandboxes into four groups: the first two classes are readily available in current products on the market, and we compare them by evaluating some important characteristics we identify in this work. The second group of two sandboxes includes novel architectures we propose, for which solutions still need to be customized ad-hoc. To help users choose the right solution for them, we refine this categorization by defining three distinct use cases for these sandboxes. Their core features can improve the isolation and scalability of the last two new architectures. © 2025 Copyright for this paper by its authors.

关键词： Malware Analysis Sandbox architectures Sandboxes Comparison Sandboxing techniques

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FPGA-ACCELERATED SIMULATION TECHNOLOGY RESEARCH TO UNLOCKING POWERFUL COMPUTATIONAL CAPABILITIES

FPGA-ACCELERATED SIMULATION TECHNOLOGY RESEARCH TO UNLOCKING...

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2024 International conference on Electrical Engineering and Intelligent Control, EEIC 2024

作者： Ji, Wenyu Department of Electrical and Electronic Engineering University of Nottingham Ningbo China Ningbo315154 China

ISBN: (纸本)9781837242672

Conventional software-based simulation methodologies sometimes face challenges in keeping pace with the increasing intricacy and scale of contemporary computing problems. This article examines the ability of FPGA-accelerated simulation technologies to meet the increasing requirements of contemporary computing. Field-programmable gate arrays (FPGAs) provide parallel processing capabilities and a reconfigurable architecture, providing a notable edge over conventional software-based simulation techniques. This results in enhanced speed, accuracy, and flexibility. The research examines the historical progression and present developments in FPGA technology, emphasizing its utilization in diverse fields such as multiphysics simulations, power systems, and machine control systems. The efficacy of FPGA acceleration in improving simulation performance is showcased using case studies and practical examples. Although there are difficulties associated with the intricate nature of FPGA design and its integration with current systems, the outlook for FPGA-accelerated simulations is optimistic. This is due to developments in AI-specific cores, heterogeneous computing, and the availability of cloud-based FPGA services, which are expected to facilitate wider acceptance and usage. This study asserts that FPGA-accelerated simulation technology is currently leading the way in computational innovation. It offers crucial tools to address the intricacy and magnitude of modern computational difficulties. © The Institution of Engineering & Technology 2024.

关键词： Reconfigurable architectures

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