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16th workshop on general purpose processing using graphics processing Unit, GPGPU 2024

ISBN: (纸本)9798400707766

The proceedings contain 5 papers. The topics discussed include: accelerating stencil computations on a GPU by combining using tensor cores and temporal blocking;exploring page-based RDMA for irregular GPU workloads: a case study on NVMe-backed GNN execution;GPU-acceleration of neighborhood-based dimensionality reduction algorithm EmbedSOM;cache cohort GPU scheduling;and regular expressions on modern GPGPUs.

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proceedings of the 15th workshop on general purpose processing Using GPU, GPGPU 2023

Proceedings of the 15th Workshop on General Purpose Processi...

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15th Annual workshop on general purpose processing using graphics processing Unit, GPGPU 2023

ISBN: (纸本)9798400707766

The proceedings contain 7 papers. The topics discussed include: GPU auto-tuning framework for optimal performance and power consumption;LATOA: load-aware task offloading and adoption in GPU;understanding portability of automotive workload: a case study with the points-to-image kernel in SYCL on heterogeneous computing platforms;simple out of order core for GPGPUs;lightweight register file caching in collector units for GPUs;exploiting scratchpad memory for deep temporal blocking: a case study for 2D Jacobian 5-point iterative stencil kernel (j2d5pt);and understanding scalability of multi-GPU systems.

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Near LLC Versus Near Main Memory processing 22

Near LLC Versus Near Main Memory Processing

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14th Annual workshop on general purpose processing using graphics processing Unit (GPGPU)

作者： Bitalebi, Hossein Geraeinejad, Vahid Ebrahimi, Masoumeh KTH Royal Inst Technol Stockholm Sweden

ISBN: (纸本)9781450393485

Emerging advanced applications, such as deep learning and graph processing, with enormous processing demand and massive memory requests call for a comprehensive processing system or advanced solutions to address these requirements. Near data processing is one of the promising structures targeting this goal. However, most recent studies have focused on processing instructions near the main memory data banks while ignoring the benefits of processing instructions near other memory hierarchy levels such as LLC. In this study, we investigate the near LLC processing structures, and compare it to the near main memory processing alternative, specifically in graphics processing units. We analyze these two structures on various applications in terms of performance and power. Results show a clear benefit of near LLC processing over near main memory processing in a class of applications. Further, we suggest an architecture, which could benefit from both near main memory and near LLC processing structures, but requiring the applications to be characterized in advance or at run time.

关键词： Near data processing processing near main memory processing near LLC GPU Irregular memory accesses

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Evaluation of the Effectiveness of Co-Processors GPU-Based in Solving of Generating Sea Waves in the Operation Simulation Model of Unmanned Maritime Vehicles

Evaluation of the Effectiveness of Co-Processors GPU-Based i...

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2023 International Russian Automation Conference, RusAutoCon 2023

作者： Fomina, Ekaterina Mironov, Andrey Pacific National University Department of Computer Engineering Khabarovsk Russia

ISBN: (纸本)9798350345551

The article considers the matters of developing the models of the bottom sonar survey applying unmanned surface vehicles. The purpose of the work is the assessment of the efficiency of applying available firmware means to conduct computer-intense calculations when using simulation model. Within the work, the main attention was paid to considering the process of forming the sea surface at various parameters of the environment as one of the most resource-intense in the simulation model from the point of view of computation efforts. It is shown that the whole process of the sea surface forming can be kept to the determined stages. The result of the process of forming is a map of the surface peaks. The sea surface forming process can be performed both in sequential and parallel form, whereat some computing blocks can be performed with use of distributed systems. The work has carried out the estimation of the calculation time in implementing the sequential process on the general-purpose processing units of architecture x86 applying OpenCV library, and also of the parallel process applying Nvidia graphics processing units supported by the CUDA technology. The computational experiments conducted for various general-purpose processing units and graphic processors issued during the period from 2010 to 2021 has shown that the use of graphic computing units allows increasing the speed of performing the stage of the complex values of frequencies amplitudes by 20 times, while in performing the stage of an inverse Fourier transform the speed is increased 3 times at average. © 2023 IEEE.

关键词： graphics processing unit

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Analysis of GPU Memory Allocation Characteristics 16

Analysis of GPU Memory Allocation Characteristics

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16th workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2025

作者： Rodriguez, Marcos Yarza, Irune Kosmidis, Leonidas Calderón, Alejandro J. Ikerlan Technology Research Center Mondragón Spain Universitat Politécnica de Catalunya Barcelona Spain Spain

ISBN: (纸本)9783959773638

The number of applications subject to safety-critical regulations is on the rise, and consequently, the computing requirements for such applications are increasing as well. This trend has led to the integration of general-purpose graphics processing units (GPGPUs) into these systems. However, the inherent characteristics of GPGPUs, including their black-box nature, dynamic allocation mechanisms, and frequent use of pointers, present challenges in certifying these applications for safety-critical systems. This paper aims to shed light on the unique characteristics of GPU programs and how they impact the certification process. To achieve this goal, several allocation methods are rigorously evaluated to determine which one is best suited to an application, regarding the program characteristics within the safety-critical domain. By conducting this evaluation, we seek to provide insights into the complexities of GPU memory accesses and its compatibility with safety-critical requirements. The ultimate objective is to offer recommendations on the most appropriate allocation method based on the unique needs of each application, thus contributing to the safe and reliable integration of GPGPUs into safety-critical systems. © Marcos Rodriguez, Irune Yarza, Leónidas Kosmidis, and Alejandro J. Calderón.

关键词： graphics processing unit

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Programming Model Extensions for general-purpose processing-In-Memory 39

Programming Model Extensions for General-Purpose Processing-...

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39th International Conference on High Performance Computing, ISC High Performance 2024

作者： Hong, Hyesun Sommer, Lukas Kim, Bongjun Kashkarov, Mikhail Narasimhan, Kumudha Veselov, Ilya Goli, Mehdi Kim, Jaeyeon Castro, Ruyman Reyes Jung, Hanwoong Samsung Advanced Institute of Technology Korea Republic of Codeplay Software Ltd. United Kingdom Samsung Electronics Russia Intel United Kingdom

ISBN: (纸本)9783982633602

The performance of many applications is limited by the available memory bandwidth. One approach to improve the performance of such memory-bound applications is to move the computation closer to the required data. processing In Memory (PIM) integrates computational units directly with the memory. To enable PIM technology in widely used programming models, we propose extensions to OpenMP and OpenACC, two examples of directive-based programming models, as well as SYCL. The extensions are designed to be portable across many existing and future parallel computing devices and platforms, making PIM technology widely available. For the extensions, we propose an end-to-end compilation framework based on several steps of abstraction and progressive lowering. To achieve this goal, we formulate a new PIM IR and conduct optimizations tailored to hardware characteristics. By using AMD MI100 GPU with PIM-enabled HBM2 memory, we observe a performance improvement of 1.2-2.1 times for representative examples and a real high-performance computing (HPC) application compared to the same GPU without PIM-enabled memory. © 2024 Research Paper proceedings of the ISC High Performance 2024. All rights reserved.

关键词： graphics processing unit

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Study on CPU and FPGA in Artificial Intelligence and Machine Learning 13

Study on CPU and FPGA in Artificial Intelligence and Machine...

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13th International Conference of Information and Communication Technology, ICTech 2024

作者： Zhou, Peng School of Electrical and Computer Engineering Nang Fang College Guangzhou China

ISBN: (纸本)9798350376258

—This article provides a comprehensive examination of the roles played by Central processing units (CPUs) and Field-Programmable Gate Arrays (FPGAs) in the realms of Artificial Intelligence (AI) and Machine Learning (ML), with a particular emphasis on the superiorities of FPGA over CPU in certain aspects. It is observed that CPUs, while versatile, fall short in aspects such as power efficiency, handling the intricacies of deep learning models, and performing large-scale matrix computations. FPGAs, on the other hand, are lauded for their remarkable flexibility, low latency, superior energy efficiency, and inherent parallelism — qualities that are immensely beneficial in AI and ML applications. The article delves into the real-world applications of both CPUs and FPGAs, showcasing specific scenarios where each excels. For instance, the low latency advantage of FPGAs is crucial in image processing tasks, where quick, efficient processing can be pivotal. In contrast, CPUs are better suited for smaller-scale or general-purpose computing tasks where flexibility and ease of programming are key. This contrast highlights the nuanced roles that these technologies play in the broader context of AI and ML. Further, the article contrasts CPUs and FPGAs in terms of architecture, design philosophy, and suitability for various AI and ML workloads. While CPUs offer a general-purpose solution with a well-established ecosystem, FPGAs provide a customizable platform that can be tailored to specific needs, offering a more efficient solution for certain types of computational tasks in AI and ML. This comparison not only sheds light on the inherent strengths and weaknesses of each technology but also underscores the importance of choosing the right tool for specific AI and ML applications, thereby optimizing performance, efficiency, and power consumption. ©2024 IEEE.

关键词： graphics processing unit

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Evaluating the Soft Error Resilience of Graph Applications on GPGPUs 10

Evaluating the Soft Error Resilience of Graph Applications o...

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10th IEEE Conference on Big Data Security on Cloud, BigDataSecurity 2024

作者： Wei, Xiaohui Zhou, Mengting Jiang, Nan Yue, Hengshan Jilin University College of Computer Science and Technology Changchun China

ISBN: (纸本)9798350389524

general-purpose graphics processing units (GPGPUs) are widely utilized for graph processing thanks to their high throughput, massive parallelism and powerful computing capacity. However, due to the increasing integration, GPGPUs are susceptible to soft errors, which can undermine the reliability of graph applications accelerated using GPGPUs. Typically, fault tolerance strategies such as thread replication and checkpoint mechanism are applied to ensure the reliability of program execution. However, these techniques require appropriate trade-off between reliability improvement and overhead. To this end, it is imperative to understand the error resilience profile of graph applications. In this paper, we construct a multidimensional analysis framework, which analyzes the error resilience of graph applications on GPGPUs from application, kernel function, and thread perspective. Based on the exhaustive statistical fault injection (FI) results for four graph algorithms, we propose heuristic suggestions as guidance for efficient fault tolerance strategies. © 2024 IEEE.

关键词： graphics processing unit

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Mpache: Interaction Aware Multi-level Cache Bypassing on GPUs 25

Mpache: Interaction Aware Multi-level Cache Bypassing on GPU...

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30th Asia and South Pacific Design Automation Conference, ASP-DAC 2025

作者： Xi, Mengyue Guo, Tianyu Huang, Xuanteng Lin, Zejia Zhang, Xianwei Sun Yat-sen University Guangzhou China

ISBN: (纸本)9798400706356

graphics processing units (GPUs) are essential for general-purpose applications and are commonly leveraging multi-level caches to alleviate memory access pressure. However, the default cache management may lose opportunities for optimal performance in different applications. Although existing cache bypassing techniques tend to address this challenge, these methods predominantly concentrate on single-level cache, thus restricting their potential for further enhancements. To mitigate this issue, we propose Mpache, a novel software-based mechanism designed to bypass multi-level caches based on the characterization of load instructions. Mpache constructs an interaction graph and analyzes the cooperation and contention among instructions. Then, the profiling data of bypassing effectiveness guides Mpache to select the appropriate cache levels to bypass for each instruction. Finally, the design is integrated into the compiler to enable automatic bypassing for existing workloads. Evaluations on off-the-shelf GPUs show that Mpache achieves an average 1.15× speedup over the default cache policy, and effectively outperforms prior arts. © 2025 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： graphics processing unit

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Designing and prototyping extensions to the Message Passing Interface in MPICH

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INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2024年第5期38卷 527-545页

作者： Zhou, Hui Raffenetti, Ken Guo, Yanfei Gillis, Thomas Latham, Robert Thakur, Rajeev Argonne Natl Lab Math & Comp Sci 9700 S Cass Ave Lemont IL 60439 USA

As HPC system architectures and the applications running on them continue to evolve, the MPI standard itself must evolve. The trend in current and future HPC systems toward powerful nodes with multiple CPU cores and multiple GPU accelerators makes efficient support for hybrid programming critical for applications to achieve high performance. However, the support for hybrid programming in the MPI standard has not kept up with recent trends. The MPICH implementation of MPI provides a platform for implementing and experimenting with new proposals and extensions to fill this gap and to gain valuable experience and feedback before the MPI Forum can consider them for standardization. In this work, we detail six extensions implemented in MPICH to increase MPI interoperability with other runtimes, with a specific focus on heterogeneous architectures. First, the extension to MPI generalized requests lets applications integrate asynchronous tasks into MPI's progress engine. Second, the iovec extension to datatypes lets applications use MPI datatypes as a general-purpose data layout API beyond just MPI communications. Third, a new MPI object, MPIX_Stream, can be used by applications to identify execution contexts beyond MPI processes, including threads and GPU streams. MPIX stream communicators can be created to make existing MPI functions thread-aware and GPU-aware, thus providing applications with explicit ways to achieve higher performance. fourth, MPIX Streams are extended to support the enqueue semantics for offloading MPI communications onto a GPU stream context. Fifth, thread communicators allow MPI communicators to be constructed with individual threads, thus providing a new level of interoperability between MPI and on-node runtimes such as OpenMP. Lastly, we present an extension to invoke MPI progress, which lets users spawn progress threads with fine-grained control to adapt the communication performance to their application designs. We describe the design and implem

关键词： Distributed computing message passing interface message passing interface plus threads message passing interface plus graphics processing units MPICH

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