A new technique, called inter-band compensated prediction, for coding colour and multispectral images is presented. It is suitable to use for coding any spectral domain and can code colour and multispectral images wit...
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A new technique, called inter-band compensated prediction, for coding colour and multispectral images is presented. It is suitable to use for coding any spectral domain and can code colour and multispectral images with any number of bands. This technique is based on the same principles as the very efficient motion compensated prediction largely used in video coding. Thus, each band is predicted in the spectral direction by compensating the differences in the neighbouring bands and then coding the prediction error spatially by another method. This is a forward adaptive prediction and the information used for compensation is coded as side information with prediction error. The comparison of the coding results with the state-of-the-art coding algorithms, based on spectral transformations, proves that this technique is very efficient and can even outperform them. In addition, compensation can be combined with any spatial coder that allows lossless, lossy and scalable coding of any spectral content of the image. It has also the advantages of being simple to implement and to use with parallelarchitectures.
We present a system for direct parallel optical data communication between integrated circuits on neighboured printed circuit boards based on a monolithic integrated CMOS smart pixel array, fibre arrays, and VCSELs. T...
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ISBN:
(纸本)0819453765
We present a system for direct parallel optical data communication between integrated circuits on neighboured printed circuit boards based on a monolithic integrated CMOS smart pixel array, fibre arrays, and VCSELs. The advantage of our system versus backplane systems is the direct data transfer through the space avoiding planar and area consuming interconnections. The detector chip allows a data rate of 625 Mbit/s per link and is cycled by an optical clock. A simulation of the chip layout showed 260 % more performance versus electrical off-chip interconnects. In principle an 8x8 data transfer is feasible allowing a data rate of 40 Gbit/s. The detector combines an optical receiver array with a digital processor array which executes imageprocessing algorithms. The optical receiver is formed by a PIN photodiode with a diameter of 40 mum, a transimpedance amplifier (TIA) and a decision-making postamplifier. The measured responsivity of the photodiode without antireflection coating is R=0.382 A/W at an optical wavelength of 670 nm. The TIA consists of a CMOS inverter and a PMOS transistor forming the feedback resistor. Together with the postamplifier, formed by a chain of five CMOS inverters and attaining digital CMOS levels, a data rate of 625 Mbit/s is achieved.
Embedded Block Coding with Optimized Truncation (EBCOT) algorithm plays a basic and crucial part in JPEG2000 still image compression system. This paper proposes a VLSI architecture of EBCOT, in which a Dynamic Memory ...
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ISBN:
(纸本)078037889X
Embedded Block Coding with Optimized Truncation (EBCOT) algorithm plays a basic and crucial part in JPEG2000 still image compression system. This paper proposes a VLSI architecture of EBCOT, in which a Dynamic Memory Control (DMC) strategy is used to reduce 60% scale of the on-chip wavelet coefficients storage. A parallel architecture is proposed to speed-up the coding process. This architecture can be used as a compact and efficient IP core for JPEG2000 VLSI implementation and various real-time image&video applications.
The Euclidean distance transform (EDT) is an important tool in image analysis. Previous work on computation of EDT is limited to sequential algorithms and parallel algorithms on general purpose architectures. The auth...
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The Euclidean distance transform (EDT) is an important tool in image analysis. Previous work on computation of EDT is limited to sequential algorithms and parallel algorithms on general purpose architectures. The authors develop a fast parallel algorithm that is amenable for VLSI implementation. The VLSI architecture is presented. Results of implementation of the VLSI design in a commercial package are also presented, and confirm the speed and suitability of the new method for real-time applications.
In this paper, we have designed an efficient parallel algorithm for performing 3 D image reconstruction. In our framework, we have considered 3 D image to be reconstructed from a series of 2 D images, produced using U...
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In this paper, we have designed an efficient parallel algorithm for performing 3 D image reconstruction. In our framework, we have considered 3 D image to be reconstructed from a series of 2 D images, produced using Ultrasonography, Computer Tomography, etc. The paper discusses a general parallel algorithm for 3 D image reconstruction over CRCW, CREW and EREW PRAM models. We have developed efficient implementations of this algorithm over a vector machines, a distributed system comprising of a cluster of Work Stations and various interconnection network like mesh network and reconfigurable bus network. The performance of the above algorithms are tested using simulation experiments performed for 3 D image reconstruction of the vitreous region of the eye using ophthalmic ultrasonograms. A novel approximation scheme has also been proposed for a drastic improvement in performance for specific kinds of image. Results indicate the time complexities of the algorithms are in resonance with expected theoretical values and image obtained has a uncompromising level of accuracy.
The proceedings contains 15 papers from the ieecolloquium on High Performance architectures for Real-time imageprocessing. Topics discussed include: three dimensional reconfigurable imageprocessing elements;process...
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The proceedings contains 15 papers from the ieecolloquium on High Performance architectures for Real-time imageprocessing. Topics discussed include: three dimensional reconfigurable imageprocessing elements;processor architecture exploiting instruction level parallelism (ILP) with reduced instruction word;generic scalable imageprocessingarchitectures;real-time multiscale convolution;discrete cosine transform cores;optical-flow detection;embedded imageprocessing;specific pole placement techniques;real-time face recognition;real-time domain detection;real-time color transformation architecture;interactive medical imageprocessing systems;and feature extraction algorithms.
The DAP Gamma II is a single instruction multiple data (SIMD) computer of either 1024 or 4096 processors which can be used as a component in a real-time system. The DAP can be programmed in a mix of high level languag...
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The DAP Gamma II is a single instruction multiple data (SIMD) computer of either 1024 or 4096 processors which can be used as a component in a real-time system. The DAP can be programmed in a mix of high level languages (Fortran Plus and C++), low level languages, and library functions. For easy development and signal applications, there is also a development system based on Khoros. Various high-speed I/O interfaces are supported, however, the DAP contains a sufficiently large memory to allow sequences of whole-image operations to be performed without any intermediate I/O.
This paper presents the design of a general-purpose, real-time imageprocessing architecture, required for developing proof of principle demonstrations of military imageprocessing applications. The main requirements ...
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This paper presents the design of a general-purpose, real-time imageprocessing architecture, required for developing proof of principle demonstrations of military imageprocessing applications. The main requirements of the architecture are to provide a scaleable, modular parallelprocessing framework, with very high bandwidth (at least 64 MByte s-1) point to point interprocessor communications. The architecture is heterogeneous, and a particular combination of processors may be chosen according to the application. A strong emphasis has been placed on the use of open standards, both for the hardware and software, and, where possible, COTS products are used.
The paper presents an interactive segmentation system that uses a parallelprocessing architecture. Poor contrasts, variable tissue properties and complex-shaped structures make the isolation of meaningful regions of ...
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The paper presents an interactive segmentation system that uses a parallelprocessing architecture. Poor contrasts, variable tissue properties and complex-shaped structures make the isolation of meaningful regions of interest difficult. The interactive approach uses the human user's knowledge base to assist in image segmentation. The measurement of regions of interest enable the resultant output image to be quantified for clinical purposes. The graphical user interface - developed under Microsoft Windows - incorporates a mouse driven interactive display. A transputer based parallelprocessing engine is provided for the computationally intensive tasks of the system. These modules of the system communicate with each other using the Windows Dynamic Data Exchange (DDE) model.
The proceedings contain 10 papers. Among the topics discussed are: color imageprocessing and its industrial and biomedical applications;microprocessor chips;character recognition;pattern recognition;algorithms;parall...
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The proceedings contain 10 papers. Among the topics discussed are: color imageprocessing and its industrial and biomedical applications;microprocessor chips;character recognition;pattern recognition;algorithms;parallelprocessing systems;pipeline processing systems;optical signal processing;parallel volume rendering;and transputer networks.
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