The York Probabilistic Automata Machine is a video rate 256 cube Automata Array. The system has been developed primarily in ASIC based components, with the bulk of processing performed through a set of overlapped pipe...
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The York Probabilistic Automata Machine is a video rate 256 cube Automata Array. The system has been developed primarily in ASIC based components, with the bulk of processing performed through a set of overlapped pipelines. Physical connectivity is limited to 128 nodes (in three dimensions), although higher 'virtual connectivities' are possible. Individual operations permitted at cellular level include binary and 'fuzzy' logic, plus simple weighted arithmetic. To complement the processor configuration, high bandwidth I/O and display units are currently under development, allowing arbitrary mappings of data I/O onto three dimensional surfaces within the unit. This paper introduces the York PAM and develops the application of virtual connectivity in automata like systems for massively parallel computation. The design and implementation of the individual processing element are presented, and the design of the three dimensional video re-sequencer discussed. Finally the use of probabilistic automata for the presentation of high level image data and facial recognition through neural techniques are presented.< >
imageprocessing, and especially real time imageprocessing, is naturally a very compute intensive task. These tasks can now be tackled very well with the Texas Instruments TMS320C40 DSP processor. This, as well as ha...
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imageprocessing, and especially real time imageprocessing, is naturally a very compute intensive task. These tasks can now be tackled very well with the Texas Instruments TMS320C40 DSP processor. This, as well as having a powerful processing architecture well suited to data intensive signal processing tasks such as imageprocessing, also has six high speed communication ports for transferring data between C40 processors in a network. Coupled with suitable modular C40 based hardware such as that from Loughborough Sound images, this can provide an extremely powerful and flexible imageprocessing system. This paper presents some results of using C40 processors in practical imageprocessing systems, both a single C40 and multiple C40s. It deals with the real processing speed achievable and techniques to achieve that speed, then the speed of transferring image data between C40s, for example partitioning a grabbed image across to several C40s. It then goes on to demonstrate how an application was developed making use of the above techniques, to give a real time imageprocessing system processing a full 512*512 image at 12.5 frames per second.< >
The authors have developed binary optical logic planes, based on nonlinear interference filters, and used them to construct basic demonstration optical processing systems. The logic planes are based on thermally sensi...
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The authors have developed binary optical logic planes, based on nonlinear interference filters, and used them to construct basic demonstration optical processing systems. The logic planes are based on thermally sensitive dielectric interference filters with external absorbers, known as BEAT devices (bistable etalons with absorbed transmission). They are operated as three-port gates. The processing scheme currently explored derives from the (electronic) cellular logic image processor. It consists of a parallel optical coprocessor operating in single instruction multiple data stream mode, controlled by a conventional electronic host computer. By programming both the Boolean logic operations carried out in the processing unit and the responses of the threshold unit on each cycle, a wide range of binary imageprocessing functions can be built up over a number of iterations using a system of this type.< >
An ever increasing amount of map data for the world's land masses is held in digital format. The computational demands of producing images in an acceptable time can be met by using high performance and low cost pa...
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An ever increasing amount of map data for the world's land masses is held in digital format. The computational demands of producing images in an acceptable time can be met by using high performance and low cost parallelprocessing machines so that new algorithms can be rapidly prototyped and tested. Such an approach has been made feasible by the use of transputer systems. There are a number of conventional algorithms which take digital surface data and process it to produce the required images. Most current algorithms are inherently sequential and do not, in general, map easily onto parallel processor architectures. The authors show that by careful algorithm design the problem can be mapped onto a number of processors by exploiting the fact that a calculation for one area is not dependent on any other data manipulations other than its own and hence can proceed independently. The algorithm is based on ray casting.< >
Vector quantization (VQ) has been extensively applied in image coding systems due to its high compression rate and simple decoder. A new algorithm of VQ based on minimum mean absolute error (MMAE) which is suitable fo...
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ISBN:
(纸本)7543909405
Vector quantization (VQ) has been extensively applied in image coding systems due to its high compression rate and simple decoder. A new algorithm of VQ based on minimum mean absolute error (MMAE) which is suitable for VLSI implementation is proposed in this paper. In the proposed algorithm, a criterion based on sum inequality of distortion measure, the presorted codebook, the nearest neighbors searching algorithm and a dichotomy searching method have been used. All of these methods result in a considerable reduction in the complexity of VLSI implementation.
We present a system for direct parallel optical data communication between integrated circuits on neighboured printed circuit boards based on a monolithic integrated CMOS smart pixel array, fibre arrays, and VCSELs. T...
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ISBN:
(纸本)0819453765
We present a system for direct parallel optical data communication between integrated circuits on neighboured printed circuit boards based on a monolithic integrated CMOS smart pixel array, fibre arrays, and VCSELs. The advantage of our system versus backplane systems is the direct data transfer through the space avoiding planar and area consuming interconnections. The detector chip allows a data rate of 625 Mbit/s per link and is cycled by an optical clock. A simulation of the chip layout showed 260 % more performance versus electrical off-chip interconnects. In principle an 8x8 data transfer is feasible allowing a data rate of 40 Gbit/s. The detector combines an optical receiver array with a digital processor array which executes imageprocessing algorithms. The optical receiver is formed by a PIN photodiode with a diameter of 40 mum, a transimpedance amplifier (TIA) and a decision-making postamplifier. The measured responsivity of the photodiode without antireflection coating is R=0.382 A/W at an optical wavelength of 670 nm. The TIA consists of a CMOS inverter and a PMOS transistor forming the feedback resistor. Together with the postamplifier, formed by a chain of five CMOS inverters and attaining digital CMOS levels, a data rate of 625 Mbit/s is achieved.
Digital filters with linear or almost linear phase are required in many applications including video, sonar and imageprocessing. A direct design approach is reported here which can be applied to 1-D and M-D filter de...
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Digital filters with linear or almost linear phase are required in many applications including video, sonar and imageprocessing. A direct design approach is reported here which can be applied to 1-D and M-D filter design so long as the filter structure is a parallel combination of allpass subfilters (PCAS). PCAS filters are used because of their low complexity and roundoff noise as well as their ability to realise non-minimum phase transfer functions. The filter design will be shown to reduce to the solution of two sets of linear simultaneous equations. Examples are given in both the 1-D and 2-D case to illustrate the method.< >
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