Optical flows (OF) have achieved greater accuracy over large speeds by improvements in implementation. Unfortunately, the improvements require the processing of more image frames or larger spatial regions. General-pur...
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Optical flows (OF) have achieved greater accuracy over large speeds by improvements in implementation. Unfortunately, the improvements require the processing of more image frames or larger spatial regions. General-purpose multicomputers can be deployed to reduce the timings recorded on workstations either in algorithmic development work or in repeatedly finding the OF field over many sets of image sequences. Four methods are parallelized but are not unusual amongst the OF methods in being amenable to data-farming. parallelizing a number of routines in a systematic manner is possible if a generalized framework is available like what is provided by the pipelined processor farming (PPF) methodology and knowledge of common structure to OF methods.
A real-time hardware color transformation system is presented. It employs two field programmable gate arrays (FPGA), an interconnecting device, combinatorial logic, and flash memory devices for the implementation of l...
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A real-time hardware color transformation system is presented. It employs two field programmable gate arrays (FPGA), an interconnecting device, combinatorial logic, and flash memory devices for the implementation of look-up tables (LUT). Its attraction is that the same general hardware structure can be used to implement any transformation, all that needs to be modified are the matrix coefficients and LUT contents. This architecture is a very powerful front-end to imageprocessing systems, where the imageprocessing can be considerably simplified by choosing the appropriate color representation.
A comparison between the Texas Instruments TMS320C80 programmable digital signal processor and a Xilinx field programmable gate array (FPGA) is presented for implementing a multiscale convolution (MSC) algorithm. The ...
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A comparison between the Texas Instruments TMS320C80 programmable digital signal processor and a Xilinx field programmable gate array (FPGA) is presented for implementing a multiscale convolution (MSC) algorithm. The merits and the disadvantages of each implementation are discussed. The MSC algorithm is useful in imageprocessing because it allows the detection of targets within images, where the scale of the target is unknown.
There is an increasing number of applications of automated image analysis in which imaging is part of an instrumentation or process control system. Such embedded applications often require performance to be tuned in v...
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There is an increasing number of applications of automated image analysis in which imaging is part of an instrumentation or process control system. Such embedded applications often require performance to be tuned in various ways to satisfy time constraints, which may vary through the lifetime of the application. They may be a requirement to produce versions of an imaging product targeted at different classes of user, to satisfy various market niches. It is important to develop software tools to easily target a variety of computational engines. The application of hardware compilation technology in a field programmable gate array (FPGA)-based system to some typical imageprocessing tasks is presented.
The real time hardware architecture of a deterministic video echo canceller (deghoster) system is presented. The deghoster is capable of calculating all the multipath channel distortion characteristics from terrestria...
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The real time hardware architecture of a deterministic video echo canceller (deghoster) system is presented. The deghoster is capable of calculating all the multipath channel distortion characteristics from terrestrial and cable television in one single pass while performing real time video in-line ghost cancellation. The results from the actual system are also presented in this paper.
A discrete cosine transform (DCT) generator is presented which facilitates the rapid design of application specific DCT cores. These can be used for the VLSI synthesis of system level multimedia IC's. The transfor...
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A discrete cosine transform (DCT) generator is presented which facilitates the rapid design of application specific DCT cores. These can be used for the VLSI synthesis of system level multimedia IC's. The transforms produced are portable across many silicon foundries and worked examples confirm that the cores are comparable in area, performance and power consumption to those based on more conventional methods. Design times are reduced by several orders of magnitude. No constraints are placed on the DCT point size and area/speed trade-offs can be rapidly computed and analyzed.
A 64-bit computer processor architecture capable of performing a maximum of eight instructions per cycle, but with an instruction word much shorter, is presented. These performances are obtained through the addressing...
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A 64-bit computer processor architecture capable of performing a maximum of eight instructions per cycle, but with an instruction word much shorter, is presented. These performances are obtained through the addressing of 128 registers storing the most frequently executed instructions. It is shown that the drawback of the instruction register file (IRF) initialization is not significant for digital signal processing applications. In combination with a high-speed external memory, this operation is even much faster than the instruction cache initialization necessary in every traditional very long instruction word (VLIW) architecture. For this reason, indirect reduced instruction set computing represents a solution for extending the application of VLIW.
imageprocessing is generally computationally intensive, and has, traditionally, required high-speed ASICs to produce acceptable real-time speeds. The use of a general-purpose computer (GPC) allows simple verification...
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imageprocessing is generally computationally intensive, and has, traditionally, required high-speed ASICs to produce acceptable real-time speeds. The use of a general-purpose computer (GPC) allows simple verification of an algorithm, but not usually real-time processing. Using an ASIC accelerator with a GPC can yield good performance, however it may have limited functionality due to the pre-defined architecture of the ASIC. Here we present a novel, general-purpose, real-time, re-configurable hardware accelerator with an architecture suitable for rapid imageprocessing. The system, developed as part of an EPSRC-funded project, will also be implemented as a single `device' using 3D multi-chip module technology.
In this paper, we design a simple and efficient VLSI architecture for a novel very fast high performance three step search (FHTSS) algorithm that is superior to the existing three step search (TSS) algorithm in all ca...
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In this paper, we design a simple and efficient VLSI architecture for a novel very fast high performance three step search (FHTSS) algorithm that is superior to the existing three step search (TSS) algorithm in all cases and also to the recently proposed new three step search (NTSS) algorithm when used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the proposed architecture can successfully implement the FHTSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three step search algorithms.
The DAP Gamma II is an SIMD computer of either 1024 or 4096 processors (PEs) which can be used as a component in a real-time system. The DAP can be programmed in a mix of high level languages (Fortran-Plus and C++), l...
The DAP Gamma II is an SIMD computer of either 1024 or 4096 processors (PEs) which can be used as a component in a real-time system. The DAP can be programmed in a mix of high level languages (Fortran-Plus and C++), low level languages, and library functions. For easy development of image and signal applications, there is also a development system based on Khoros. Various high-speed I/O interfaces are supported, however the DAP contains a sufficiently large memory to allow sequences of whole-image operations to be performed without any intermediate I/O.
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