Digital filters with linear or almost linear phase are required in many applications including video, sonar and imageprocessing. A direct design approach is reported here which can be applied to 1-D and M-D filter de...
详细信息
Digital filters with linear or almost linear phase are required in many applications including video, sonar and imageprocessing. A direct design approach is reported here which can be applied to 1-D and M-D filter design so long as the filter structure is a parallel combination of allpass subfilters (PCAS). PCAS filters are used because of their low complexity and roundoff noise as well as their ability to realise non-minimum phase transfer functions. The filter design will be shown to reduce to the solution of two sets of linear simultaneous equations. Examples are given in both the 1-D and 2-D case to illustrate the method.< >
A hardware architecture for an adaptive loss-less data compressor is described. The architecture is suitable for implementation on a single ASIC. The architecture results from an investigation aimed at developing nove...
详细信息
A hardware architecture for an adaptive loss-less data compressor is described. The architecture is suitable for implementation on a single ASIC. The architecture results from an investigation aimed at developing novel compression algorithms that can utilise the fine-grain parallelprocessing capabilities of VLSI integrable structures and hence, achieve high performance. The efficiency of different hardware structures are assessed for text, image and machine code data compression through simulation. Suitable candidate designs based around a shifting content-addressable memory (CAM) array are identified. A design for one such option is developed using a commercial CAD package. Despite using modest 2-mu-M CMOS technology, compressed data is produced at a minimum rate of 100 Mbit/s. the design are presented.
The recognition of two-dimensional images is important in many diverse areas of application ranging from character recognition to automatic industrial inspection and medical imageprocessing, and many possible approac...
详细信息
The recognition of two-dimensional images is important in many diverse areas of application ranging from character recognition to automatic industrial inspection and medical imageprocessing, and many possible approaches to system design for such applications exist. Because of the inherently parallel nature of the algorithms conventionally adopted in classification processing, many recent attempts to improve the flexibility and effectiveness of classifier design have focused on the implementation level, exploiting parallelarchitectures to provide a judicious match to task specification. There is, however, considerable interest in developing new parallelarchitectures based on neural network designs which can be applied to practical classification tasks.< >
Describes the use of a heterogeneous Multiple-SIMD (M-SIMD) array architecture for the tracking of features within images. Features are detected within the input images and tracked through subsequent images. Tracking ...
详细信息
Describes the use of a heterogeneous Multiple-SIMD (M-SIMD) array architecture for the tracking of features within images. Features are detected within the input images and tracked through subsequent images. Tracking filters with appropriate kinematic models, run in parallel with the imageprocessing on this architecture. Example tracking models and algorithms are used to illustrate the benefits that can be provided by an M-SIMD architecture over existing array architectures.< >
The paper introduces the generalised hierarchical massively parallel system (MPS) and extends data transfer parallelism to all members of the memory hierarchy. Methods are presented for connecting multiple parallel di...
详细信息
The paper introduces the generalised hierarchical massively parallel system (MPS) and extends data transfer parallelism to all members of the memory hierarchy. Methods are presented for connecting multiple parallel disks and parallel memory modules to the generalised hierarchical MPS. Full utilisation of data transfer bandwidth between disks and processing elements is facilitated by structuring and corner turning the incoming data before storing it on parallel disks. One major application of MPSs is imageprocessing. The methods presented perform well on image data. The total system is generalised by introducing architectural parameters. Varying these parameters allows the system to be represented as various forms of SIMD architecture. A new SIMD massively parallel system, BLITZEN, is used as an example to illustrate some of the concepts presented.
British Aerospace (Space Systems) Ltd. is currently developing an integrated digital signal and imageprocessing architecture for the European Space Agency. It is intended that this multiprocessor architecture will be...
详细信息
British Aerospace (Space Systems) Ltd. is currently developing an integrated digital signal and imageprocessing architecture for the European Space Agency. It is intended that this multiprocessor architecture will become an open system standard for demanding space-based applications. The architecture is also directly applicable to many ground-based imageprocessing applications. This paper presents the rationale behind the development of the integrated DSP/IP architecture and describes the various facets of the architecture (interprocessor communications, processing elements and control philosophy).< >
Describes the architecture of the ELSA Processor, a massively parallel SIMD/MSIMD machine implemented in wafer scale technology, and its capability to implement many algorithms in imageprocessing, pattern recognition...
详细信息
Describes the architecture of the ELSA Processor, a massively parallel SIMD/MSIMD machine implemented in wafer scale technology, and its capability to implement many algorithms in imageprocessing, pattern recognition, signal processing, etc. The ELSA Processor contains 2304 bit serial processing elements (PEs) configured in a two dimensional array. The wafer employs a 1.2 mu m double metal CMOS process and will operate at a clock speed of up to 20 MHz. For eight bit data, additions can be carried out at about 5 billion per second.< >
A transputer network is used for visual texture analysis. The image is segmented and farmed amongst the transputers of the network. The analysis is based on fractal texture measurements, modified to be suitable for no...
详细信息
A transputer network is used for visual texture analysis. The image is segmented and farmed amongst the transputers of the network. The analysis is based on fractal texture measurements, modified to be suitable for non-fractal visual texture from natural scenes. Gravity feed dynamic load-balancing is used for data distribution, with software written in a modular fashion to facilitate changes in topology. Various array and tree topologies are evaluated and compared. Timing comparison is used to identify and eliminate bottlenecks and 94% efficiency is achieved using an array of 16 slave transputers.< >
parallelarchitectures have yet to achieve the generality of sequential processing, particularly in areas such as imageprocessing and vision. The main reason why parallelprocessing does not exhibit the same generali...
详细信息
parallelarchitectures have yet to achieve the generality of sequential processing, particularly in areas such as imageprocessing and vision. The main reason why parallelprocessing does not exhibit the same generality as sequential processing is because a large number of new degrees of freedom have been introduced for both the compiler writer and programmer. They include class of architecture, topology, programming paradigm reconfiguration, and the number of processors to be used. The complex relationship between these factors in typical real-time vision applications, makes performance estimation almost impossible and thus encourages a heuristic design philosophy. The authors approach is to fix some of these degrees of freedom to constrain the parallel architecture so that performance estimation is feasible. In this paper it is shown that, although not optimal in all areas, tree topologies of distributed processors with point-to-point communication links (e.g. the transputer) offer the best compromise between generality, performance and cost.< >
暂无评论