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检索条件"任意字段=Proceedings of the IEEE Workshop on Advances in Parallel and Distributed Systems"

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Execution of typical scientific applications on Globus-based Grids

Execution of typical scientific applications on Globus-based...

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proceedings - ISPDC 2004: Third International Symposium on parallel and distributed Computing/HeteroPar '04: Third International workshop on Algorithms, Models and Tools for parallel Computing on Heterogeneous Networks

作者： Herrera, J. Huedo, E. Montero, R.S. Llorentet, I.M. Dpto. Arquitectura de Computadores y Automática Facultad de Informática Universidad Complutense 2 8040 Madrid Spain 28850 Torrejón de Ardoz Spain

ISBN: (纸本)0769522106

One of the barriers that prevents the expansion and adoption of Grid technologies is the lack of a standard programming paradigm to port existing applications among different environments. The distributed Resource Management Application API (DRMAA) has been proposed to aid the rapid development and distribution of these applications across the Grid. In this paper we present the first implementation of the DRMAA standard on a Globus-based testbed, and show its suitability to express typical scientific applications. As a case of study, we will consider in this paper the implementation of the NAS Grid Benchmarks with DRMAA. The DRAL4A routines are supported by the functionality offered by the GridWay framework, that provides the runtime mechanisms needed for transparently executing jobs on a dynamic Grid environment. © 2004 ieee.

关键词： distributed computer systems

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Dynamic scheduling of parallel jobs with QoS demands in multiclusters and grids 04

Dynamic scheduling of parallel jobs with QoS demands in mult...

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proceedings - Fifth ieee/ACM International workshop on Grid Computing

作者： He, Ligang Jarvis, Stephen A. Spooner, Daniel P. Chen, Xinuo Nudd, Graham R. Department of Computer Science University of Warwick Coventry CV4 7AL United Kingdom

ISBN: (纸本)0769522564

This paper addresses the dynamic scheduling of parallel jobs with QoS demands (soft-deadlines) in multiclusters and grids. Three metrics (over-deadline, makespan and idle-time) are combined with variable weights to evaluate the scheduling performance. These three metrics are used to measure the extent of the jobs' QoS demand compliance, the resource throughput and the resource utilization. Two levels of performance optimisation are applied in the multicluster. At the multicluster level, a scheduler (which we call MUSCLE) allocates parallel jobs with high packing potential to the same cluster;it also takes the jobs' QoS requirements into account and employs a heuristic to allocate suitable workloads to each cluster to balance the overall system performance. At the single cluster level, an existing workload manager, called TITAN, utilizes a genetic algorithm to further improve the scheduling performance of the jobs previously allocated by MUSCLE. Extensive experimental studies are conducted to verify the effectiveness of the scheduling mechanism as well as the effect of the prediction accuracy on the scheduling performance. The results show that compared with traditional distributed workload allocation policies, the comprehensive scheduling performance of parallel jobs is significantly improved across the multicluster, and the presence of prediction errors does not dramatically weaken the performance advantage. © 2004 ieee.

关键词： parallel processing systems

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A configurable Mu itiprocessor and dynamic load balancing for parallel LU factorization

A configurable Mu itiprocessor and dynamic load balancing fo...

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proceedings - 18th International parallel and distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)

作者： Wang, Xiaofang Ziavras, Sotirios G. Department of Electrical Engineering New Jersey Institute of Technology Newark NJ 07102

ISBN: (纸本)0769521320

The exponentially increasing complexity of many scientific applications and the high cost of supercomputing force us to explore new, sustainable, and affordable high-performance computing platforms. Recent significant advances in FPGA technology and the inherent advantages of configurable logic have brought about new research efforts in the configurable computing field: parallel processing on configurable chips. We explore here parallel LU factorization of large sparse block-diagonal-bordered (BDB) matrices on a configurable multiprocessor that we have designed and implemented. A dynamic load balancing strategy is proposed and analyzed. Performance results for ieee power test systems are provided. Our research provides evidence that configurable logic can be a viable alternative to high-performance scientific computing.

关键词： Interconnection networks

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Support for data-intensive, variable-granularity grid applications via distributed file system virtualization - A case study of light scattering spectroscopy

Support for data-intensive, variable-granularity grid applic...

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2nd International workshop on Challenges of Large Applications in distributed Environments (CLADE 2004)

作者： Paladugula, J Zhao, M Figueiredo, RJ Univ Florida ACIS Lab Dept Elect & Comp Engn Gainesville FL 32611 USA

ISBN: (纸本)0769521150

A key challenge faced by large-scale, distributed applications in Grid environments is efficient, seamless data management. In particular, for applications that can benefit from access to data at variable granularities, data management can pose additional programming burdens to an application developer. This paper presents a case for the use of virtualized distributed file systems as a basis for data management for data-intensive, variable-granularity applications. The approach leverages on-demand transfer mechanisms of existing, de-jacto network file system clients and servers that support transfers of partial data sets in an application-transparent fashion, and complement them with user-level performance and functionality enhancements such as caching and encrypted communication channels. The paper uses a nascent application from the medical imaging field (Light Scattering Spectroscopy - LSS) as a motivation for the approach, and as a basis for evaluating its performance. Results from performance experiments that consider the 16-processor parallel execution of LSS analysis and database generation programs show that, in the presence of data locality, a virtualized wide-area distributed file system setup and configured by Grid middleware can achieve performance levels close (13% overhead or less) to that of a local disk, and superior (up to 680% speedup) to non-virtualized distributed file systems.

关键词： distributed computer systems

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Design, implementation and performance evaluation of GridRPC programming middleware for a large-scale computational Grid 04

Design, implementation and performance evaluation of GridRPC...

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5th International workshop on Grid Computing

作者： Tanaka, Y Takemiya, H Nakada, H Sekiguchi, S AIST Grid Technol Res Ctr Tsukuba Ibaraki 3058568 Japan

ISBN: (纸本)0769522564

This paper reports on the design, implementation and performance evaluation of a suite of GridRPC programming middleware called Ninf-G Version 2 (Ninf-G2). NinfG2 is a reference implementation of the GridRPC API, a proposed GGF standard. Ninf-G2 has been designed so that it provides 1) high performance in a large-scale computational Grid, 2) the rich functionalities which are required to adapt to compensate for the heterogeneity and unreliability of a Grid environment, and 3) an API which supports easy development and execution of Grid applications. Ninf-G2 is implemented to work with basic Grid services, such as GSI, GRAM, and MDS in the Globus Toolkit version 2. The performance of Ninf-G2 was evaluated using a weather forecasting system which was developed using Ninf-G2. The experimental results indicate that high performance can be attained even in relatively fine-grained task-parallel applications on hundreds of processors in a Grid environment.

关键词： distributed computer systems

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JIST: Just-in-time scheduling translation for parallel processors

JIST: Just-in-time scheduling translation for parallel proce...

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作者： Agosta, Giovanni Reghizzi, Stefano Crespi Falauto, Gerlando Sykora, Martino Politecnico di Milano Dipartimento di Elettronica e Informazione Piazza Leonardo da Vinci 32 20133 Milano Italy

ISBN: (纸本)0769522106

The application fields of bytecode virtual machines and VLIW processors overlap in the area of embedded and mobile systems, where the two technologies offer different benefits, namely high code portability, low power consumption and reduced hardware cost. Dynamic compilation makes it possible to bridge the gap between the two technologies, but special attention must be paid to software instruction scheduling, a must for the VLIW architectures. We have implemented JJST, a Virtual Machine and JIT compiler for Java Bytecode targeted to a VLIW processor. We show the impact of various optimizations on the performance of code compiled with JIST through the experimental study on a set of benchmark programs. We report significant speedups, and increments in the number of instructions issued per cycle up to 50% with respect to the non-scheduling version of the JIT compiler. Further optimizations are discussed. © 2004 ieee.

关键词： Scheduling

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HERA: A reconfigurable and mixed-mode parallel computing engine on platform FPGAs

HERA: A reconfigurable and mixed-mode parallel computing eng...

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proceedings of the 16th IASTED International Conference on parallel and distributed Computing and systems

作者： Wang, Xiaofang Ziavras, Sotirios G. Department of Electrical Engineering New Jersey Institute of Technology Newark NJ 07102 United States

The high price, long design and development cycles, programming difficulty and high maintenance cost of supercomputers limit their range of potential applications. Recent advances in Field-Programmable Gate Arrays (FPGAs) have made feasible the development of high-performance and programmable parallel systems on a programmable chip (PSOPC). PSOPC's yield high-performance at low cost for many parallel applications. We present in this paper the design and implementation of our HERA (HEterogeneous Reconfigurable Architecture) machine that employs FPGAs to allow the simultaneous execution of a variety of parallel processing modes, including SIMD (Single-Instruction, Multiple-Data), MIMD (Multiple-Instruction, Multiple-Data) and M-SIMD (Multiple-SIMD). The processing element is centered on a single-precision ieee 754 floating-point unit (FPU) and employs a 7-stage pipeline. To demonstrate the robustness and viability of our approach, we propose a data partitioning scheme and employ mixed-mode scheduling for Cannon's matrix-matrix multiplication algorithm with matrices of arbitrary size and shape. Performance results on our 64-PE machine that employs a dual-FPGA system are better than the optimized performance on a dual-Xeon PC.

关键词： parallel processing systems

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Mapping of subtasks with multiple versions in a heterogeneous ad hoc grid environment

Mapping of subtasks with multiple versions in a heterogeneou...

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作者： Shivle, Sameer Siegel, H.J. Maciejewski, Anthony A. Banka, Tarun Chindam, Kiran Dussinger, Steve Kutruff, Andrew Penumarthy, Prashanth Pichumani, Prakash Satyasekaran, Praveen Sendek, David Sousa, J. Sridharan, Jayashree Sugavanam, Prasanna Velazco, Jose Colorado State University Electrical and Computer Engineering Dept. Fort Collins CO 80523 United States Computer Science Dept. Fort Collins CO 80523 United States HP Technologies Fort Collins CO 80528-9544 Abbott Laboratories Barceloneta 00617 Puerto Rico

ISBN: (纸本)0769522106

An ad hoc grid is a heterogeneous computing system composed of mobile devices. The problem studied here is to statically assign resources to the subtasks of an application, which has an execution time constraint, when the resources are oversubscribed. Each subtask has a preferred version, and a secondary version that uses fewer resources. The goal is to assign resources so that the application meets its execution time constraint while minimizing the number of secondary versions used. Five resource allocation heuristics to derive near-optimal solutions to this problem are presented and evaluated. © 2004 ieee.

关键词： parallel processing systems

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Optimization of the POLCOMS hydrodynamic code for terascale high-performance computers

Optimization of the POLCOMS hydrodynamic code for terascale ...

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proceedings - 18th International parallel and distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)

作者： Ashworth, M. Holt, J.T. Proctor, R. CCLRC Daresbury Laboratory Warrington WA4 4AD United Kingdom Proudman Oceanographic Laboratory Bidston Observatory Birkenhead CH43 7RA United Kingdom

ISBN: (纸本)0769521320

advances in computational science are closely tied to developments in high-performance computing. We consider the case of shelf sea modelling where models have been growing in complexity and where model domains have been growing and grid resolutions shrinking in pace with the increasing storage capacity and computing power of high-end systems. Terascale systems are now readily available with performance levels measurable in TeraFlop/s and memories counted in TeraBytes. The scientific case is now being made for regional models at 1km resolution, allowing the accurate representation of eddies, fronts and other regions containing steep gradients. The hydrodynamic model is increasingly being coupled with other models in multidisciplinary studies e.g. ecosystem modelling and wave modelling. We show that the performance attainable from the POLCOMS hydrodynamic code is measurable at about 0.5 TeraFlop/s on an IBM p690 cluster with 1024 processors. The scalability on this system and others is excellent up to 1000 processors. We describe a wide range of optimisations which have together enabled this code to reach these performance levels.

关键词： parallel processing systems

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The leading edge of production wafer probe test technology

The leading edge of production wafer probe test technology

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proceedings - International Test Conference 2004

作者： Mann, William R. Taber, Frederick L. Seitzer, Philip W. Broz, Jerry J. SWTW General Department Rockwell International Newport Beach CA 92663 BiTS Workshop General Department IBM Microelectronics LaGrangeville NY 12540 Agere Systems Allentown PA 18109 SWTW Technical Department International Test Solutions Reno NV 89523

Microelectronic wafer and die level testing have undergone significant changes in the past few years. This paper's first section describes today's leading edge characteristics for numerous areas of this test technology including the minimum I/O pad pitch, advances in contactor technologies, maximum number of I/Os probed, maximum number of die tested in parallel, the largest prober and substrates, and the maximum frequencies being tested at the wafer level. The second section will discuss the leading edge practices in three critical areas of wafer test: probe contactor cleaning, I/O pad damage minimization, and sorting good from bad die. The final section will present the communication methods between the design and the probe test organizations and some state-of-the-art examples for I/O pad designs.

关键词： WSI circuits

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