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检索条件"任意字段=Proceedings of the International Conference on Application Specific Array Processors"

共 1678 条记录，以下是91-100 订阅

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Using group theory to specify application specific interconnection networks for SIMD DSPs

Using group theory to specify application specific interconn...

引用

14th IEEE international conference on application-specific Systems, Architectures and processors

作者： Dräger, T Fettweis, GP IEEE Germany

ISBN: (纸本)076951992X

We introduce another view of group theory in the field of interconnection networks. With this approach it is possible to specify application specific network topologies for permutation data transfers. Routing of data transfers is generated and all possible permutation data transfers are guaranteed. We present the approach by means of a kind of SIMD DSP.

关键词： Interconnection networks (circuit switching)

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array Aware Training/Pruning: Methods for Efficient Forward Propagation on array-based Neural Network Accelerators 31

Array Aware Training/Pruning: Methods for Efficient Forward ...

引用

31st IEEE international conference on application-specific Systems, Architectures and processors (ASAP)

作者： Chitty-Venkata, Krishna Teja Somani, Arun K. Iowa State Univ Dept Elect & Comp Engn Ames IA 50011 USA

ISBN: (纸本)9781728171470

Due to the increase in the use of large-sized Deep Neural Networks (DNNs) over the years, specialized hardware accelerators such as Tensor Processing Unit and Eyeriss have been developed to accelerate the forward pass of the network. The essential component of these devices is an array processor which is composed of multiple individual compute units for efficiently executing Multiplication and Accumulation (MAC) operation. As the size of this array limits the amount of DNN processing of a single layer, the computation is performed in several batches serially leading to extra compute cycles along both the axes. In practice, due to the mismatch between matrix and array sizes, the computation does not map on the array exactly. In this work, we address the issue of minimizing processing cycles on the array by adjusting the DNN model parameters by using a structured hardware array dependent optimization. We introduce two techniques in this paper: array Aware Training (AAT) for efficient training and array Aware Pruning (AAP) for efficient inference. Weight pruning is an approach to remove redundant parameters in the network to decrease the size of the network. The key idea behind pruning in this paper is to adjust the model parameters (the weight matrix) so that the array is fully utilized in each computation batch. Our goal is to compress the model based on the size of the array so as to reduce the number of computation cycles. We observe that both the proposed techniques results into similar accuracy as the original network while saving a significant number of processing cycles (75%).

关键词： array Deep Neural Networks Accelerators Training Pruning

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Transformation techniques for serial array design

Transformation techniques for serial array design

引用

proceedings of the international conference on application specific array processors

作者： Luk, W.W.C. Oxford Univ Computing Lab Oxford United Kingdom

ISBN: (纸本)0818629673

This paper describes a design framework for developing application-specific serial array circuits. Starting from a description of the state-transition logic or a fully-parallel architecture, correctness-preserving transformations are employed to derive a wide range of implementations with different space-time trade-offs. The approach has been used in synthesizing designs based on Field-Programmable Gate arrays, and will be illustrated by the development of a number of circuits including sorters and convolvers.

关键词： Computer architecture

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Custom FPGA-based Soft-processors for Sparse Graph Acceleration 26

Custom FPGA-based Soft-Processors for Sparse Graph Accelerat...

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26th international conference on application-specific Systems, Architectures and processors (ASAP)

作者： Kapre, Nachiket Nanyang Technol Univ Sch Comp Engn Singapore Singapore

ISBN: (纸本)9781479919253

FPGA-based soft processors customized for operations on sparse graphs can deliver significant performance improvements over conventional organizations (ARMv7 CPUs) for bulk synchronous sparse graph algorithms. We develop a stripped-down soft processor ISA to implement specific repetitive operations on graph nodes and edges that are commonly observed in sparse graph computations. In the processing core, we provide hardware support for rapidly fetching and processing state of local graph nodes and edges through spatial address generators and zero-overhead loop iterators. We interconnect a 2D array of these lightweight processors with a packet-switched network-on-chip to enable fine-grained operand routing along the graph edges and provide custom send/receive instructions in the soft processor. We develop the processor RTL using Vivado High-Level Synthesis and also provide an assembler and compilation flow to configure the processor instruction and data memories. We outperform a Microblaze (100MHz on Zedboard) and an NIOS-II/f (100MHz on DE2-115) by 6x (single processor design) as well as the ARMv7 dual-core CPU on the Zynq SoCs by as much as 10x on the Xilinx ZC706 board (100 processor design) across a range of matrix datasets.

关键词： PROCESSOR Line graph address generator Assemblers Customs Graph algorithms performance boost Customization central processing units

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Determining longest common subsequences of two sequences on a linear array of processors

Determining longest common subsequences of two sequences on ...

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proceedings of the international conference on application specific array processors

作者： Mukherjee, Amar Univ of Central Florida Orlando United States

ISBN: (纸本)0818629673

This paper presents special-purpose linear array processor architecture for determining longest common subsequences (LCS) of two sequences. The algorithm uses systolic and pipelined architecture suitable for VLSI implementation. The algorithms are also suitable for implementation on parallel machines. We first develop a `greedy' algorithm to determine some of the LCS and then propose a generalization to determine all LCS of the given pair of sequences. Earlier hardware algorithms [Lipton and Lopresti, 85;Mukherjee, 89] were concerned with determining only the length of LCS or the edit distance of two sequences.

关键词： Algorithms

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Optimal synthesis of application specific heterogeneous pipelined multiprocessors

Optimal synthesis of application specific heterogeneous pipe...

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proceedings of the 1994 international conference on application specific array processors

作者： DeSouza-Batista, J.C. Parker, Alice C. Univ of Southern California Los Angeles United States

In this paper we present a technique and formal model for optimal synthesis of specialized heterogeneous multiprocessors, given task flow graphs to be executed in a pipelined (periodic) fashion. SOS is a formal approach to system synthesis using mixed integer-linear programming, ensuring optimally of the final solutions. SOS was extended to cover the pipelined design style. The extensions were made while trying to avoid a considerable increase in computation time over the non-pipelined case. The extensions include new binary variables as well as new constraints used to ensure numerical convergence. The present tool supports minimization of parameters such as initiation rate, latency and cost.

关键词： Pipeline processing systems

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Design of throughput-optimized arrays from recurrence abstractions

Design of throughput-optimized arrays from recurrence abstra...

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21st IEEE international conference on application-specific Systems, Architectures and processors

作者： Jacob, Arpith C. Buhler, Jeremy D. Chamberlain, Roger D. Washington Univ Dept Comp Sci & Engn St Louis MO 63130 USA

ISBN: (纸本)9781424469673

Many compute-bound applications have seen order-of-magnitude speedups using special-purpose accelerators. FPGAs in particular are good at implementing recurrence equations realized as arrays. Existing high-level synthesis approaches for recurrence equations produce an array that is latency-space optimal. We target applications that operate on a large collection of small inputs, e. g. a database of biological sequences, where overall throughput is the most important measure of performance. In this work, we introduce a new design-space exploration procedure within the polyhedral framework to optimize throughput of a systolic array subject to area and bandwidth constraints of an FPGA device. Our approach is to exploit additional parallelism by pipelining multiple inputs on an array and multiple iteration vectors in a processing element. We prove that the throughput of an array is given by the inverse of the maximum number of iteration vectors executed by any processor in the array, which is determined solely by the array's projection vector. We have applied this observation to discover novel arrays for Nussinov RNA folding. Our throughput-optimized array is 2x faster than the standard latency-space optimal array, yet it uses 15% fewer LUT resources. We achieve a further 2x speedup by processor pipelining, with only a 37% increase in resources. Our tool suggests additional arrays that trade area for throughput and are 4-5x faster than the currently used latency-optimized array. These novel arrays are 70-172x faster than a software baseline.

关键词： Systolic array Throughput Optimization Recurrences FPGA Dynamic Programming

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Realization of a nonlinear digital filter on a DSP array processor

Realization of a nonlinear digital filter on a DSP array pro...

引用

proceedings of the 1997 IEEE international conference on application-specific Systems, Architectures and processors, ASAP'97

作者： Kwan, Hercule Powers, Edward J. Swartzlander Jr., Earl E. Univ of Texas at Austin Austin United States

This paper presents the performance evaluation of a fast third-order Volterra digital filtering algorithm mapped onto an AT&T DSP-3 parallel processor. Five different implementations are considered. Speed-up results indicate that the `time-skewing' method is currently the fastest. An application to nonlinear communication channel equalization using a 64-QAM signal constellation is presented.

关键词： Digital filters

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Recent developments in configurable and extensible processors

Recent developments in configurable and extensible processor...

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17th IEEE international conference on application-specific Systems, Architectures and processors

作者： Martin, Grant Tensilica Inc Santa Clara CA USA

ISBN: (纸本)0769526829

There have been some interesting technology developments in the area of configurable and extensible processors in the last few years. This paper outlines some of the most recent technologies that we have been developing at Tensilica, including the role of fixed implementations, automatic generation of application-oriented configurations, and design methodologies including fast functional simulation. It also discusses some of our future evolution - in particular, the move from a single processor focus to a multi-processor SoC (MPSoC) focus. We conclude by outlining Some of the research problems that we find of most interest.

关键词： Program processors

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Behavioral synthesis of high performance, low cost, and low power application specific processors for linear computations

Behavioral synthesis of high performance, low cost, and low ...

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proceedings of the 1994 international conference on application specific array processors

作者： Potkonjak, Miodrag Srivastava, Mani B. NEC USA Princeton United States

Throughput has been widely traditionally recognized as the most popular performance metric for implementation of application specific computations. However, increasingly applications such as embedded controllers impose constraints on both throughput and latency as important metrics of speed. Although throughput alone can be arbitrarily improved for several classes of systems using previously published techniques, none of those approaches are effective when latency constraints are considered. DSP, communications, and control systems are often either linear, or have subsystems that are linear. Recently, an optimal technique for simultaneous optimization of throughput and latency of linear computations was introduced in [Sri94]. However, in many cases this technique introduces significant area overhead. In this paper we apply certain key aspects of that technique (on-arrival-processing and maximally fast implementation of linear computations) with exploration of state-space based transformations to develop four synthesis techniques which generate high throughput, low latency, low area, and low power application specific processors for the special case of single input linear computations. The new transformation techniques can also be used to increase the implementation efficiency while achieving the same latency and throughput as the original design - we obtained large improvements in area and power on many benchmarks when using the proposed transformations in this alternate role.

关键词： Computers

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