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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1551 条记录，以下是91-100 订阅

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An Energy-aware Spiking Neural Network hardware Mapping based on Particle Swarm Optimization and Genetic Algorithm

An Energy-aware Spiking Neural Network Hardware Mapping base...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Liu, Junxiu Huang, Xingyue Jiang, Dong Luo, Yuling Guangxi Normal Univ Sch Elect Engn Guilin Peoples R China

ISBN: (纸本)9781728191980

Spiking Neuron Network (SNN) is a biological neural network model which shows great capability in the time series data processing and pattern recognition etc. according to the recent research. It has been implemented in hardware system with a good scalability, where the Networks-on-Chip (NoC) interconnection strategy is widely used for the data communications between the neurons. The mapping between a SNN and a NoC hardware system is one of the challenge for the development of the hardware SNNs. In this paper, a hybrid Particle Swarm Optimization (PSO) algorithm for hardware SNN mapping is proposed with the object of minimizing the energy consumption. Compared to the conventional PSO, it can search the mapping solutions through three directions which can speed up the finding. In the meantime, the Genetic Algorithm (GA) is combined to provide the mutation operation to avoid converging to the local optimum. A typical hardware SNN is used as the testbench and results show that an effective hardware SNN mapping is obtained with a low energy consumption, and local optimum is avoided compared to other approaches.

关键词： Spiking neural networks hardware implementation Networks-on-Chip Energy consumption

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hardware/software codesign - Pedagogy for the industry

Hardware/software codesign - Pedagogy for the industry

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5th international conference on Information Technology - New Generations

作者： He, Min Tsai, Ming-Che Wu, Xiaolong Wang, Fei Nasr, Ramzi Calif State Univ Long Beach Dept Comp Sci & Comp Engn Long Beach CA 90840 USA Calif State Univ Long Beach Dept Elect Engn Long Beach CA 90840 USA

ISBN: (纸本)9780769530994

With the essentiality of hardware/software codesign in present and future designs, it has become more and more important to educate engineers in this area. In this paper, industry trends and expectations are investigated in the area of hardware/software codesign and system-level design, as well as its current status in education, to derive a better pedagogy for hardware/software codesign.

关键词： Computer architecture

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Work-in-Progress: Runtime Requirements Monitoring for State-based hardware

Work-in-Progress: Runtime Requirements Monitoring for State-...

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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Seo, Minjun Lysecky, Roman Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA

ISBN: (纸本)9781538655627

This paper presents a requirements-driven methodology enabling efficient runtime monitoring of hardware in embedded systems. We present a novel method for extracting hardware verification requirements from state-based hardware models to construct a hierarchical runtime monitoring graph (HRMG) that can be efficiently used at runtime to verify correctness.

关键词： Runtime requirements verification hardware verification formal verification models non-intrusive monitoring

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Towards interprocess communication and interface synthesis for a heterogenous real-time rapid prototyping environment

Towards interprocess communication and interface synthesis f...

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6th international Workshop on hardware/software codesign (CODES/CASHE 98)

作者： Fischer, F Muth, A Farber, G Tech Univ Munich Lab Process Control & Real Time Syst D-8000 Munchen Germany

ISBN: (纸本)0818684429

Rapid Prototyping has been proposed as a means to reduce development time and costs of real-rime systems. Our approach uses a heterogeneous, tightly coupled multiprocessor system based on off-the-shelf components as target architecture for an executable prototype, which is generated from the specification in an automated design process. Here, too, we aim to use existing tools and languages. But interface and communication synthesis, while being the key requirement of an automated translation of a abstract specification to a distributed system, is not yet state-of-the-art. The sensitivity of the overall performance of multiprocessor systems to overhead and latency introduced by communication on the other hand calls for an efficient interprocess communication (IPC). This paper presents concept and implementation of IPC functions which, implementing the message queue semantics of the specification language SDL, links the standard components of our multiprocessor system in an efficient manner, while at the same time providing the interface synthesis needed by the automated generation of a rapid prototype. The experiences gained when implementing a non-trivial, real-world CAN controller and monitor application on our rapid prototyping environment, are described as a first proof of concept.

关键词： communication synthesis rapid prototyping SDL hard real-time task classification model

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A practical tool box for system level communication synthesis 01

A practical tool box for system level communication synthesi...

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9th international Symposium on hardware/software codesign (CODES 2001)

作者： Hommais, D Pétrot, F Augé, I Univ Paris 06 Equipe ASIM LIP6 Paris France

ISBN: (纸本)1581133642

This paper presents a practical approach to communication synthesis for hardware/software system specified as tasks communicating through lossless blocking channels. It relies on a limited set of templates that characterize the way data an exchanged between tasks realized either in software or in hardware. The templates are highly portable because their software part is implemented using the POSIX thread functions, and their hardware part is a hand crafted synthesizable module with a system VCI interface. These Interface Modules allow simple Virtual Component reuse since they not only implement protocol compatibility through the use of the system VCI/OCB standard but also system level communications through semantics widely accepted in the design community.

关键词： hardware Permission Yarn Computer architecture Protocols Virtual manufacturing Writing Resumes

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Work-in-Progress: hardware Implementation of a Multi-Mode-Aware Mixed-Criticality Scheduler

Work-in-Progress: Hardware Implementation of a Multi-Mode-Aw...

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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Hounsinou, Sena Vasu, Aishwarya Ramaprasad, Harini Southern Illinois Univ Carbondale IL 62901 USA Univ N Carolina Charlotte NC USA

ISBN: (纸本)9781538655627

To minimize size, weight, power, and cost, the industry aims at consolidating different criticality applications on the same hardware platform. In such a mixed-criticality environment, it is challenging to contain the overhead due to potential mode changes under overload conditions. Traditional scheduler implementation at the software level introduces additional overheads due to timer interrupt processing and context switching. To minimize overall software overhead and to improve timing predictability, in this paper, we propose an implementation of the mixed-criticality scheduler in the hardware that is capable of detecting task-overruns and making mode transitions seamlessly.

关键词： Task analysis hardware Real-time systems Monitoring Registers software Processor scheduling

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system-level design automation tools for digital microfluidic biochips 05

System-level design automation tools for digital microfluidi...

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international conference on hardware/software codesign and system synthesis

作者： Chakrabarty, K Su, F Duke Univ Dept Elect & Comp Engn Durham NC 27708 USA

ISBN: (纸本)1595931619

Biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and DNA sequencing. Current full-custom design techniques for digital microfluidic biochips do not scale well for increasing levels of system integration. Analogous to classical VLSI synthesis, a top-down system-level design automation approach can shorten the biochip design cycle and reduce human effort. We present here an overview of a system-level design methodology that includes architectural synthesis and physical design. The proposed design automation approach is expected to relieve biochip users from the burden of manual optimization of bioassays.. time-consuming hardware design, and costly testing and maintenance procedures.

关键词： synthesis physical design microfluidics biochip

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Profiling in the ASP codesign environment

Profiling in the ASP codesign environment

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proceedings of the 8th international Symposium on system synthesis

作者： Parkinson, Matthew F. Parameswaran, Sri Univ of Queensland Queensland Australia

Automation of the hardware/software codesign methodology brings with it the need to develop sophisticated high-level profiling tools. This paper presents a profiling tool which uses execution profiling on standard C code to obtain accurate and consistent times at the level of individual compound code sections. This tool is used in the ASP hardware/software codesign project. The results from this tool show that profiling must be performed on dedicated hardware which is as close as possible to the final implementation, as opposed to a workstation.

关键词： Computer architecture

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hardware/software codesign for FPGA-based systems

Hardware/software codesign for FPGA-based systems

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The 1999 32nd Annual Hawaii international conference on system Sciences, HICSS-32

作者： Saul, J.M. Oxford Univ Computing Lab Oxford United Kingdom

A new codesign compiler, Dash, provides a co-synthesis and co-simulation environment for mixed FPGA/processor architectures. It compiles a C-like description to a solution containing both processors and custom hardware, and allows the descriptions of FPGA-based processors to be heavily parametrized. The user may add instructions to the processors, and the Dash software architecture allows the user to add facilities for targeting these extra instructions to the compiler. This system is being used to design a number of case studies, and a single-chip codesign of an Internet video game is used to illustrate the design flow.

关键词： Computer systems programming

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Special Session Paper: Exploiting Quality-Energy Tradeoffs with Arbitrary Quantization

Special Session Paper: Exploiting Quality-Energy Tradeoffs w...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Moreau, Thierry Augusto, Felipe Howe, Patrick Alaghi, Armin Ceze, Luis Univ Washington Seattle WA 98195 USA Univ Estadual Campinas Campinas SP Brazil

ISBN: (纸本)9781450351850

Approximate computing aims to expose and exploit quality vs. efficiency tradeoffs to enable ever-more demanding applications on energy-constrained devices such as smartphones, or IoT devices. This paper makes the case for arbitrary quantization as a compelling approximation technique that exposes quality vs. energy tradeoffs and provides practical error guarantees. We present QAPPA (Quality Autotuner for Precision Programmable Accelerators), an autotuning framework for C/C++ programs that automatically minimizes the precision of each arithmetic and memory operation to meet user defined application level quality guarantees. QAPPA integrates energy models of precision scaling mechanisms to produce bandwidth and energy savings estimates for precision scalable accelerator designs. We show that QAPPA can exploit precision scaling mechanisms to meet arbitrary user-provided quality targets on the PERFECT benchmark suite to achieve significant energy savings and memory bandwidth reduction.

关键词： Quantization (signal) Bandwidth Benchmark testing hardware Signal to noise ratio Adders Kernel

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