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Control system for a robotic walking simulator

Control system for a robotic walking simulator

引用

IEEE international conference on Robotics and Automation

作者： Schmidt, H Sorowka, D Piorko, F Marhoul, N Bernhardt, R Fraunhofer Inst IPK Div Automat & Robot D-10587 Berlin Germany

ISBN: (纸本)0780382323

The control system for a robotic walking simulator and rehabilitation device requires enhanced operation modes and control capabilities, compared to conventional industrial robot controllers. In order to be able to implement custom made algorithms at all levels of the controller and to have an extensible and reusable control environment, we decided to develop a full-featured robot control soft- and hardware, including a graphical user interface (GUI), as a modular and open system. The control system hardware comprises a standard industrial PC including different industrial I/O cards (e.g. SERCOS fieldbus). The control software runs on Linux/RTLinux and can be operated stand-alone or via an integrated real-time Ethernet communication link. It comprises a multi-threaded task architecture with asynchronous inter-process communication via a system of several FIFO queues. An important enhancement over classical industrial robot controllers is the development and implementation of a special Fourier based interpolation mode for cyclic robot trajectories, in addition to classical point to point or continuous path motion move commands. Another improvement is the interpolation of every single point of the robot motion inside the Motion Generator thread based on the current move command interpolation type, hence improving trajectory smoothness. Advanced force and impedance control algorithms are currently being implemented. The GUI runs on a separate Windows PC, which is connected to the control PC via a real-time Ethernet link, since the control PC is usually located inside the CNC cabinet. The self developed GUI software comprises a user friendly tool for graphical trajectory synthesis, an off-line real-time simulation and multiple windows for on-line data visualization in 2D and 3D. The machine should also be operated by non-technical personnel, such as physiotherapists in rehabilitation hospitals, hence major parts of the GUI layout have been designed in close cooperation

关键词： Industrial robots

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Dual-pipeline heterogeneous ASIP design 04

Dual-pipeline heterogeneous ASIP design

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： S. Radhakrishnan Hui Guo S. Parameswaran School of Computer Science & Engineering University of New South Wales Sydney Australia

ISBN: (纸本)9781581139372

We demonstrate the feasibility of a dual pipeline application specific instruction set processor. We take a C program and create a target instruction set by compiling to a basic instruction set from which some instructions are merged, while others discarded. Based on the target instruction set, parallelism of the application program is analyzed and two unique instruction sets are generated for a heterogeneous dual-pipeline processor. The dual pipe processor is created by making two unique ASIPs (VHDL descriptions) utilizing the ASIP-Meister Tool Suite, and fusing the two VHDL descriptions to construct a dual pipeline processor. Our results show that in comparison to the single pipeline application specific instruction set processor, the performance improves by 27.6% and switching activity reduces by 6.1% for a number of benchmarks. These improvements come at the cost of increased area which for benchmarks considered is 16.7% on average.

关键词： Application specific processors Pipelines Embedded system Space exploration Costs Application software VLIW Instruction sets Telephony Personal digital assistants

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CPU scheduling for statistically-assured real-time performance and improved energy efficiency 04

CPU scheduling for statistically-assured real-time performan...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Haisang Wu B. Ravindran E.D. Jensen Peng Li ECE Dept. Virginia Tech Blacksburg VA USA The MITRE Corporation Bedford MA USA

ISBN: (纸本)9781581139372

We present a CPU scheduling algorithm, called energy-efficient utility accrual algorithm (or EUA), for battery-powered, embedded real-time systems. We consider an embedded software application model where repeatedly occurring application activities are subject to deadline constraints specified using step time/utility functions. For battery-powered embedded systems, system-level energy consumption is also a primary concern. We consider CPU scheduling that (1) provides assurances on individual and collective application timeliness behaviors and (2) maximizes system-level timeliness and energy efficiency. Since the scheduling problem is intractable, EUA heuristically computes CPU schedules with a polynomial-time cost. Several properties of EUA are analytically established, including timeliness optimality during under-load situations and statistical assurances on timeliness behavior. Further, our simulation results confirm EUA's superior performance.

关键词： Energy efficiency Application software Processor scheduling Scheduling algorithm Real time systems Embedded software Embedded system Energy consumption Polynomials Costs

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Efficient search space exploration for HW-SW partitioning 04

Efficient search space exploration for HW-SW partitioning

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： S. Banerjee N. Dutt Center for Embedded Computer Systems University of California Irvine CA USA

ISBN: (纸本)9781581139372

hardware/software (HW-SW) partitioning is a key problem in the codesign of embedded systems, studied extensively in the past. One major open challenge for traditional partitioning approaches - as we move to more complex and heterogeneous SoCs - is the lack of efficient exploration of the large space of possible HW/SW configurations, coupled with the inability to efficiently scale up with larger problem sizes. We make two contributions for HW-SW partitioning of applications represented as procedural call-graphs: 1) we prove that during partitioning, the execution time metric for moving a vertex needs to be updated only for the immediate neighbours of the vertex, rather than for all ancestors along paths to the root vertex; consequently, we observe faster run-times for move-based partitioning algorithms such as simulated annealing (SA), allowing call graphs with thousands of vertices to be processed in less than a second, and 2) we devise a new cost function for SA that allows frequent discovery of better partitioning solutions by searching spaces overlooked by traditional SA cost functions. We present experimental results on a very large design space, where several thousand configurations are explored in minutes as compared to several hours or days using a traditional SA formulation. Furthermore, our approach is frequently able to locate better design points with over 10 % improvement in application execution time compared to the solutions generated by a Kernighan-Lin partitioning algorithm starting with an all-SW partitioning.

关键词： Space exploration Partitioning algorithms Cost function hardware Embedded software Embedded system Runtime Simulated annealing Extraterrestrial measurements Algorithm design and analysis

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Efficient exploration of on-chip bus architectures and memory allocation 04

Efficient exploration of on-chip bus architectures and memor...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Sungchan Kim Chaeseok Im Soonhoi Ha School of Electrical Engineering and Computer Science Seoul National University Seoul South Korea

ISBN: (纸本)9781581139372

Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and mapping. We present an iterative two-step exploration methodology for bus-based on-chip communication architecture and memory allocation, assuming that memory traces from the processing elements are given from the mapping stage. The proposed method uses a static performance estimation technique to reduce the large design space drastically and quickly, and applies a trace-driven simulation technique to the reduced set of design candidates for accurate performance estimation. Since local memory traffic as well as shared memory traffic are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. The viability and efficiency of the proposed methodology are validated by two real-life examples, 4-channel digital video recorder (DVR) and an equalizer for OFDM DVB-T receiver.

关键词： Memory architecture Computer architecture system-on-a-chip Space exploration Traffic control Design methodology Permission Computer science Iterative methods Video sharing

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Detecting overflow detection 04

Detecting overflow detection

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： V. Kotlyar M. Moudgill Sandbridge Technologies Inc. White Plains NY USA

ISBN: (纸本)9781581139372

Fixed-point saturating arithmetic is widely used in media and digital signal processing applications. A number of processor architectures provide instructions that implement saturating operations. However, standard high-level languages, such as ANSI C, provide no direct support for saturating arithmetic. Applications written in standard languages have to implement saturating operations in terms of basic two's complement operations. In order to provide fast execution of such programs it is important to have an optimizing compiler automatically detect and convert appropriate code fragments to hardware instructions. We present a set of techniques for automatic recognition of saturating arithmetic operations. We show that in most cases the recognition problem is simply one of Boolean circuit equivalence. Given the expense of solving circuit equivalence, we develop a set of practical approximations based on abstract interpretation. Experiments show that our techniques, while reliably recognizing saturating arithmetic, have small compile-time overhead. We also demonstrate that our approach is not limited to saturating arithmetic, but is directly applicable to recognizing other idioms, such as add-with-carry and absolute value.

关键词： software libraries Digital arithmetic Fixed-point arithmetic Digital signal processing ANSI standards Circuits Computer languages Permission High level languages Optimizing compilers

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Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures 04

Efficient mapping of hierarchical trees on coarse-grain reco...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： F. Rivera M. Sanchez-Elez M. Fernandez R. Hermida N. Bagherzadeh Departmento de Arquitectura de Computadores y Automática Universidad Computadores Madrid Spain Depto. de Arquitectura de Computadores y Automática Universidad Complutense Madrid SPAIN Dept. of Electrical and Computing Engineering University of California Irvine CA USA

ISBN: (纸本)9781581139372

Reconfigurable architectures have become increasingly important in years. We present an approach to the problem of executing 3D graphics interactive applications onto these architectures. The hierarchical trees are usually implemented to reduce the data processed, thereby diminishing the execution time. We have developed a mapping scheme that parallelizes the tree execution onto a SIMD reconfigurable architecture. This mapping scheme considerably reduces the time penalty caused by the possibility of executing different tree nodes in SIMD fashion. We have developed a technique that achieves an efficient hierarchical tree execution taking decisions at execution time. It also promotes the possibility of data coherence in order to reduce the execution time. The experimental results show high performance and efficient resource utilization on tested applications.

关键词： Vegetation mapping Reconfigurable architectures Computer architecture Tree graphs Application software Streaming media Digital signal processing Permission Graphics Resource management

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Fast cosimulation of transformative systems with OS support on SMP computer

Fast cosimulation of transformative systems with OS support ...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Zhengting He A. Mok Department of Electrical & Computer Engineering University of Texas Austin Austin TX USA Department of Computer Science University of Texas Austin Austin TX USA

Transformative applications are a class of dataflow computation characterized by iterative behavior. The problem of partitioning a transformative application specification to a set of available hardware (HW) and software (SW) processing elements (PEs) and derivation of a job execution order (scheduling) on them has been quite well studied, but the problem of obtaining fast simulation of these applications poses different constraints. In this paper, we propose an efficient framework for a symmetric multi-processor (SMP) simulation host to achieve fast HW/SW co-simulation for transformative applications, given the partition solutions and the derived schedulers. The framework overcomes the limitations in existing Linux SMP kernel and requires only a reasonable amount of modifications to it. We also present a heuristic algorithm which effectively assigns simulation tasks to the processors on the simulation host, considering both average job simulation time on each processor and other simulation overhead. Our experiments show that the algorithm is able to find satisfactory suboptimal solutions with very little computation time. Based on the task assignment solution, the simulation time can be reduced by 25% to 50% from the obvious but naive approach.

关键词： Operating systems Computational modeling Application software Permission Codecs Helium hardware Processor scheduling Linux Kernel

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hardware-software co-design of resource constrained systems on a chip

Hardware-software co-design of resource constrained systems ...

引用

international conference on Distributed Computing systems Workshop

作者： N. Thepayasuwan A. Doboli Department of Electrical and Computer Engineering State University of New York Stony Brook Stony Brook NY USA

We present a hardware-software codesign methodology for resource constrained SoC fabricated in a deep submicron process. The novelty of the methodology consists in contemplating critical hardware and layout aspects during system level design for latency optimization. The effect of interconnect parasitic and delays is considered for characterizing bus speed and data communication times. The methodology permits coarse and medium grained resource sharing across tasks for execution speedup through superior usage of hardware. We offer experiments for the proposed codesign methodology, including a JPEG SoC.

关键词： hardware system-on-a-chip Delay Communication system control system-level design Data communication Resource management Computer architecture Embedded system Partitioning algorithms

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Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures 04

Fast cycle-accurate simulation and instruction set generatio...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： S.J. Weber M.W. Moskewicz M. Gries C. Sauer K. Keutzer University of California Electronics Research Lab Berkeley USA Infineon Technologies Corporate Research Munich Germany

ISBN: (纸本)9781581139372

State-of-the-art architecture description languages have been successfully used to model application-specific programmable architectures limited to particular control schemes. We introduce a language and methodology that provide a framework for constructing and simulating a wider range of architectures. The framework exploits the fact that designers are often only concerned with data paths, not the instruction set and control. In the framework, each processing element is described in a structural language that only requires the specification of the data path and constraints on how it can be used. From such a description, the supported operations of the processing clement are automatically extracted and a controller is generated. Various architectures are then realized by composing the processing elements. Furthermore, hardware descriptions and bit-true cycle-accurate simulators are automatically generated. Results show that our simulators are up to an order of magnitude faster than other reported simulators of this type and two orders of magnitude faster than equivalent Verilog simulations.

关键词： Computational modeling Data mining Automatic generation control Automatic control Architecture description languages hardware design languages Computer simulation Permission Computer architecture Computer languages

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