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Benchmark-based design strategies for single chip heterogeneous multiprocessors 04

Benchmark-based design strategies for single chip heterogene...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： J.M. Paul D.E. Thomas A. Bobrek Electrical and Computer Engineering Department Carnegie Mellon University Pittsburgh PA USA

ISBN: (纸本)9781581139372

Single chip heterogeneous multiprocessors are arising to meet the computational demands of portable and handheld devices. These computing systems are not fully custom designs traditionally targeted by the design automation (DA) community, general purpose designs traditionally targeted by the computer architecture (CA) community, nor pure embedded designs traditionally targeted by the real-time (RT) community. An entirely new design philosophy will be needed for this hybrid class of computing. The programming of the device will be drawn from a narrower set of applications with execution that persists in the system over a longer period of time than for general purpose programming. But the devices will still be programmable, not only at the level of the individual processing element, but across multiple processing elements and even the entire chip. The design of other programmable single chip computers has enjoyed an era where the design trade-offs could be captured in simulators such as SimpleScalar and performance could be evaluated to the SPEC benchmarks. Motivated by this, we describe new benchmark-based design strategies for single chip heterogeneous multiprocessors. We include an example and results.

关键词： Application software Computer architecture Computational modeling Design automation Design optimization Bandwidth Application specific integrated circuits Embedded system Embedded computing Benchmark testing

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Memory system design space exploration for low-power, real-time speech recognition 04

Memory system design space exploration for low-power, real-t...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Rajeev Krishna S. Mahlke T. Austin Advanced Computer Architecture Laboratory University of Michigan Ann Arbor USA

ISBN: (纸本)9781581139372

The recent proliferation of computing technology has generated new interest natural I/O interface technologies such as speech recognition. Unfortunately, the computational and memory demands of such applications currently prohibit their use on low-power portable devices in anything more than their simplest forms. Previous work has demonstrated that the thread level concurrency inherent in this application domain can be used to dramatically improve performance with minimal impact on overall system energy consumption, but that such benefits are severely constrained by memory system bandwidth. This work presents a design space exploration of potential memory system architectures. A range of low-power memory organizations are considered, from conventional caching to more advanced system-on-chip implementations. We find that, given architectures able to exploit concurrency in this domain, large L2 based cache hierarchies and high bandwidth memory systems employing data stream partitioning and on-chip embedded DRAM and ROM technologies can provide much of the performance of idealized memory systems without violating the power constraints of the low-power domain.

关键词： Space exploration Real time systems Speech recognition Concurrent computing Bandwidth system-on-a-chip Space technology Portable computers Yarn Energy consumption

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Development methodology of ASIP based on Java byte code using HW/SW co-design system for processor design

Development methodology of ASIP based on Java byte code usin...

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international conference on Distributed Computing systems Workshop

作者： H. Yanagisawa M. Uehara H. Mori Department of Information and Computer Science Toyo University Japan

To develop an ASIP (application specific instruction set processor), development of HW (hardware) and development of SWDE (software development environments) are required. Separate develops of HW and SWDE in a short time are difficult. So HW/SW codesign system is necessary rapid develop of ASIPs. We have developed C-DASH(c-like design automation shell), which is a HW/SW codesign system for designing processors based on ISA (instruction set architecture). We describe the HW/SW codesign system C-DASH, along with a description of a Java processor that directly executes Java byte code is given as an example.

关键词： Application specific processors Java Process design Embedded system Application software Instruction sets hardware Programming Design automation Computer architecture

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Dynamic overlay of scratchpad memory for energy minimization 04

Dynamic overlay of scratchpad memory for energy minimization

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international conference on hardware/software codesign and system synthesis (CODES)

作者： M. Verma L. Wehmeyer P. Marweclel Department of Computer Science XII University of Dortmund Dortmund Germany Technische Universitat Dortmund Dortmund Nordrhein-Westfalen DE Dept. of Comput. Sci. Dortmund Univ. Germany

ISBN: (纸本)9781581139372

The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing the energy consumption of the memory subsystem. Consequently, novel memories as well as novel algorithms for their efficient utilization are being designed. Scratchpads are known to perform better than caches in terms of power, performance, area and predictability. However, unlike caches they depend upon software allocation techniques for their utilization. We present an allocation technique which analyzes the application and inserts instructions to dynamically copy both code segments and variables onto the scratchpad at runtime. We demonstrate that the problem of dynamically overlaying scratchpad is an extension of the global register allocation problem. The overlay problem is solved optimally using ILP formulation techniques. Our approach improves upon the only previously known allocation technique for statically allocating both variables and code segments onto the scratchpad. Experiments report an average reduction of 34% and 18% in the energy consumption and the runtime of the applications, respectively. A minimal increase in code size is also reported.

关键词： Scanning probe microscopy Embedded system Runtime Permission Computer science Algorithm design and analysis Application software Memory management Power system management Energy dissipation

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Analyzing heap error behavior in embedded JVM environments 04

Analyzing heap error behavior in embedded JVM environments

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international conference on hardware/software codesign and system synthesis (CODES)

作者： G. Chen M. Kandemir N. Vijaykrishnan A. Sivasubramaniam M.J. Irwin Department of Computer Science and Engineering Pennsylvania State University University Park PA USA

ISBN: (纸本)9781581139372

Recent studies have shown that transient hardware errors caused by external factors such as alpha particles and cosmic ray strikes can be responsible for a large percentage of system down-time. Denser processing technologies, increasing clock speeds, and low supply voltages used in embedded systems can worsen this problem. In many embedded environments, one may not want to provision extensive error protection in hardware because of (i) form-factor or power consumption limitations, and/or (ii) to keep costs low. Also, the mismatch between the hardware protection granularity and the field access granularity can lead to false alarms and error cancellations. Consequently, software-based approaches to identify and possibly rectify these errors seem to be promising. Towards this goal, This work specifically looks to enhance the software's ability to detect heap memory errors in a Java-based embedded system. Using several embedded Java applications, This work first studies the tradeoffs between reliability, performance, and memory space overhead for two schemes that perform error checks at object and field granularities. We also study the impact of object characteristics (e.g., lifetime, re-use intervals, access frequency, etc.) on error propagation. Considering the pros and cons of these two schemes, we then investigate two hybrid strategies that attempt to strike a balance between memory space and performance overheads and reliability. Our experimental results clearly show that the granularity of error protection and its frequency can significantly impact static/dynamic overheads and error detection ability.

关键词： Error analysis hardware Embedded system Power system protection Java Frequency Alpha particles Clocks Low voltage Energy consumption

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A loop accelerator for low power embedded VLIW processors 04

A loop accelerator for low power embedded VLIW processors

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international conference on hardware/software codesign and system synthesis (CODES)

作者： B. Mathew A. Davis School of Computing University of Utah Salt Lake UT USA

ISBN: (纸本)9781581139372

The high transistor density afforded by modern VLSI processes has enabled the design of embedded processors that use clustered execution units to deliver high levels of performance. However, delivering data to the execution resources in a timely manner remains a major problem that limits ILP. It is particularly significant for embedded systems where memory and power budgets are limited. A distributed address generation and loop acceleration architecture for VLIW processors is presented. This decentralized on-chip memory architecture uses multiple SRAMs to provide high intra-processor bandwidth. Each SRAM has an associated stream address generator capable of implementing a variety of addressing modes in conjunction with a shared loop accelerator. The architecture is extremely useful for generating application specific embedded processors, particularly for processing input data which is organized as a stream. The idea is evaluated in the context of a fine grain VLIW architecture executing complex perception algorithms such as speech and visual feature recognition. Transistor level Spice simulations are used to demonstrate a 159x improvement in the energy delay product when compared to conventional architectures executing the same applications.

关键词： VLIW Very large scale integration Process design Embedded system Distributed power generation Acceleration Memory architecture Bandwidth Random access memory Speech analysis

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Fast exploration of bus-based on-chip communication architectures 04

Fast exploration of bus-based on-chip communication architec...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： S. Pasricha N. Dutt M. Ben-Romdhane Center for Embedded Computer Systems University of California Irvine CA USA Center for Embedded Computer Systems University of California Irvine CA Conexant Systems Inc. Newport Beach CA USA

ISBN: (纸本)9781581139372

As a result of improvements in process technology, more and more components are being integrated into a single system-on-chip (SoC) design. Communication between these components is increasingly dominating critical system paths and frequently becomes the source of performance bottlenecks. It therefore becomes extremely important for designers to explore the communication space early in the design flow. Traditionally, pin-accurate bus cycle accurate (PA-BCA) models were used for exploring the communication space. To speed up simulation, transaction based bus cycle accurate (T-BCA) models have been proposed, which borrow concepts found in the transaction level modeling (TLM) domain. The cycle count accurate at transaction boundaries (CCATB) modeling abstraction was introduced for fast communication space exploration. In This work, we describe the mechanisms that produce the speedup in CCATB models and demonstrate the effectiveness of the CCATB exploration approach with the aid of a case study involving an AMBA 2.0 based SoC subsystem used in the multimedia application domain. We also analyze how the achieved simulation speedup scales with design complexity and show that SoC designs modeled at the CCATB level simulate 120% faster than PA-BCA and 67% faster than T-BCA models on average.

关键词： Space exploration system-on-a-chip Computer architecture Space technology Analytical models Permission Embedded computing Multiprocessing systems Application specific integrated circuits High level languages

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Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation 04

Modeling operation and microarchitecture concurrency for com...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Xinping Zhu Wei Qin S. Malik Department of Electrical Engineering Princeton University Princeton NJ USA

ISBN: (纸本)9781581139372

In multiprocessor based SoCs, optimizing the communication architecture is often as important as, if not more than, optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of computation architectures, the same is not true for the communication architectures. A major challenge in modeling the communication architecture is managing the concurrency at multiple levels: at the operation level, multiple communication operations may be active at any time; at the microarchitecture level, several microarchitectural components may be operating in parallel. Further, it is important to be able to clearly specify how the operation level concurrency maps to the microarchitectural level concurrency. This work presents a modeling methodology and a retargetable simulation framework which fill this gap. This framework seeks to facilitate the design space exploration of the communication sub-system through a rigorous modeling approach based on a formal concurrency model, the operation state machine (OSM). We first introduce the basic notions and concepts of OSM and show by example how this model can be used to represent the inherent concurrency in the architecture and microarchitecture of processors. Then we demonstrate the applicability of OSM in modeling on-chip communication architectures (OCAs) by walking though a router based packet switching network example and a bus example. Due to the fact that the OSM model is naturally suited to handle the operation and microarchitecture level concurrencies of OCAs as well, our OSM-based modeling methodology enables the entire system including both the computation and communication architectures to be modeled in a single OSM framework. This allows us to develop a tool set that can synthesize cycle-accurate system simulators for multi-PE SoC prototypes. To demonstrate the flexibility of this methodology, we choose two distinct system configurations with different types of OCA:

关键词： Microarchitecture Concurrent computing Computer architecture Computational modeling Communication system operations and management Space exploration Network-on-a-chip Legged locomotion Packet switching Network synthesis

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Power analysis of system-level on-chip communication architectures 04

Power analysis of system-level on-chip communication archite...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： K. Lahiri A. Raghunathan NEC Laboratories of America Inc. Princeton NJ USA

ISBN: (纸本)9781581139372

For complex system-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumption. Managing and optimizing this important component of SoC power requires a detailed understanding of the characteristics of its power consumption. Various power estimation and low-power design techniques have been proposed for the global interconnects that form part of SoC communication architectures (e.g., low-swing buses, bus encoding, etc). While effective, they only address a limited part of communication architecture power consumption. A state-of-the-art communication architecture, viewed in its entirety, is quite complex, comprising several components, such as bus interfaces, arbiters, bridges, decoders, and multiplexers, in addition to the global bus lines. Relatively little research has focused on analyzing and comparing the power consumed by different components of the communication architecture. In this work, we present a systematic evaluation and analysis of the power consumed by a state-of-the-art communication architecture (the AMBA on-chip bus), using a commercial design flow. We focus on developing a quantitative understanding of the relative contributions of different communication architecture components to its power consumption, and the factors on which they depend. We decompose the communication architecture power into power consumed by logic components (such as arbiters, decoders, bus bridges), global bus lines (that carry address, data, and control information), and bus interfaces. We also perform studies that analyze the impact of varying application traffic characteristics, and varying SoC complexity, on communication architecture power. Based on our analyses, we evaluate different techniques for reducing the power consumed by the on-chip communication architecture, and compare their effectiveness in achieving power savings at the system level. In addition to quanti

关键词： system-on-a-chip Energy consumption Bridges Decoding Energy management Power system management Power system interconnection Encoding Multiplexing Logic

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Analytical models for leakage power estimation of memory array structures 04

Analytical models for leakage power estimation of memory arr...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： M. Mamidipaka K. Khouri N. Dutt M. Abadir Center for Embedded Computer Systems University of California Irvine CA USA Global Strategy and Future Tools & Meth. Freescale/Motorola Inc. Austin TX USA

ISBN: (纸本)9781581139372

There is a growing need for accurate power models at the system level. Memory structures such as caches, branch target buffers (BTBs), and register files occupy significant area in contemporary SoC designs and are the main contributors to system leakage power dissipation. Existing models for leakage power estimation in array structures typically use coefficients derived from elaborate SPICE simulations. However, these methodologies are not applicable to array designs in a newer technology, that require power estimates early in the design cycle. In this paper, we propose analytical models for array structures that are based only on high level design parameters. Assuming typical circuit implementation styles, we identify the transistors that contribute to the leakage power in each array sub-circuit and develop models as a function of the operation (read/write/idle) on the array and organizational parameters of the array. The developed models are validated by comparing their estimates against the leakage power measured using SPICE simulations on industrial array designs belonging to the e500 processor core. The comparison shows that the models are accurate with an error margin of less than 21.5% and thus can be used in high-level power-performance exploration. Interestingly, in array designs with dual threshold voltage technology, we observed that contrary to the general expectation, the array memory core contributes to just 9% and the address decoder contributes to as much as 62% of the total leakage power.

关键词： Analytical models Power dissipation Power system modeling SPICE Embedded computing Registers Circuit simulation Power measurement Threshold voltage Decoding

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