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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

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Using invariants to optimize formal specifications before code synthesis

Using invariants to optimize formal specifications before co...

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proceedings - 2nd ACM and IEEE international conference on Formal Methods and Models for Co-Design, MEMOCODE'04

作者： Jeffords, Ralph D. Leonard, Elizabeth I. Washington DC 20375 United States

ISBN: (纸本)0780385098

Formal specifications of required system behavior can be analyzed, verified, and validated, giving high confidence that the specification captures the desired behavior. Transferring this confidence to the system implementation depends on a formal link between requirements and implementation. The automatic generation of provably correct code provides just such a link. While optimization is usually performed on code to achieve efficiency, we propose to optimize the formal specification before generating code, thus providing optimization independent of the particular code generation method. This paper investigates the use of invariants in optimizing code generated from formal specifications in the software Cost Reduction (SCR) tabular notation. We show that invariants (1) provide the basis for simplifying expressions that otherwise cannot be improved using traditional compiler optimization techniques, and (2) allow detection and elimination of parts of the specification that would lead to unreachable code. © 2004 IEEE.

关键词： Computer hardware description languages

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A Platform-based SoC hardware/software Co-Design Environment

A Platform-based SoC Hardware/Software Co-Design Environment

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The 8th international conference on Computer Supported Cooperative Work in Design(第八届计算机支持的协同工作设计国际会议)(CSCWD2004)

作者： Zhihui Xiong Sikun Li Jihua Chen Dawei Wang School of Computer Science National University of Defense TechnologyChangshaP.R.China410073

ISBN: (纸本)0780379411

This paper presents a Platform-based SoChardware/software co-design environment namedHSCDE. It introduces the overall structure of HSCDE,describes the Platform-based SoC system modelingtechnology, ant algorithm based hardware/softwarepartitioning technology and Hierarchical DirectedAcyclic Graph based performance constraintassignment technology. HSCDE supports Platform-based SoC hardware/software co-design *** supports almost all the design phases from SoCsystem modeling to RTL level SoC system. It dividesSoC hardware/software co-design into system modelinglevel (level 1), virtual components level (level 2) andreal components level (level 3), and it performs the 2mappings among the 3 design levels by DesignPlanning (mapping 1) and Virtual-Real synthesis(mapping 2). We have clone SoC system design for MP3player SoC, MEPG2 player SoC and CDMA wirelesscommunication SoC in HSCDE environment. Resultsshow that HSCDE effectively supports Platform-basedSoC hardware/software co-design methodology;itenhanced system reuse of existing SoC design. Statisticsindicate an average of 10％～25％ revisions on platformtemplates for a new SoC design, and we achievedplatform template reuse ratio by 75％～90％.

关键词： hardware-software codesign system-on-chip directed graphs logic design integrated circuit design SoC hardware-software codesign HSCDE SoC system modeling hardware-software partitioning hierarchical directed acyclic graph performance constraint assignment technology RTL level SoC system virtual components level virtual-real synthesis MP3 player SoC MEPG2 player SoC CDMA wireless communication SoC

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A Novel Deadlock Avoidance Algorithm and Its hardware Implementation 04

A Novel Deadlock Avoidance Algorithm and Its Hardware Implem...

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proceedings of the international conference on hardware/software codesign and system synthesis: 2004

作者： Jaehwan Lee Vincent John Mooney III Georgia Institute of Technology

ISBN: (纸本)9781581139372

This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provides a mechanism for very fast and automatic deadlock avoidance in MultiProcessor system-on-a-Chip (MPSoC) with multiple (e.g., 10) processing elements and multiple (e.g., 40) resources. The DAU avoids deadlock by not allowing any grant or request that leads to a deadlock. In case of livelock, the DAU asks one of the processes involved in the livelock to release resource(s) so that the livelock can also be resolved. We simulated two realistic examples that can benefit from the DAU, and demonstrated that the DAU not only avoids deadlock in a few clock cycles but also achieves a 37% speed-up of application execution time over avoiding deadlock in software. Finally, the SoC area overhead due to the DAU is small, under 0.01% in our example.

关键词： Algorithms

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Performance analysis of embedded systems in the virtual component co-design environment

Performance analysis of embedded systems in the virtual comp...

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international conference and Workshop on Engineering of Computer-Based systems

作者： P. Garg A. Gupta J.W. Rozenblit Department of Electrical and Computer Engineering University of Arizona Tucson Tucson AZ USA

Due to the increasing complexity of embedded systems in terms of functionality and architectural resources available to meet performance and cost criteria, there is an added responsibility on the designer to make the right choices. These choices can differ in terms of different hardware/software partitions, different types of architectural components, different communication architectures etc. and each choice meets certain performance metrics up to certain level. In this paper, we are exploring the design space to analyze different choices of design implementations by quantitative estimation of performance during simulation. Multicriteria decision making (MCDM) methods are used to rank our choices. To demonstrate the validity of the above exploration technique, a codesign tool from Cadence - virtual component codesign (VCC) is used. It gives us the flexibility to create the experimental frame setup and probes to measure the performance metrics during simulations. The tradeoffs between performance metrics are performed by MCDM. A safety critical example is chosen to demonstrate our approach.

关键词： Performance analysis Embedded system Measurement Space exploration Cost function hardware software performance Computer architecture Analytical models Decision making

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Keynote: cellular handset technology system requirements and integration trends 04

Keynote: cellular handset technology system requirements and...

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proceedings of the 2nd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Sven Mattisson Ericsson Mobile Platforms AB Lund Sweden

ISBN: (纸本)9781581139372

In ten years the cellular telephone has evolved from a tool for the professional to an indispensable consumer product with a very high market penetration. At the same time, the handset cost, weight, and standby time have been reduced by more than a factor of ten. These factors have been critical for the success story of the mobile *** technical aspects behind the rapid handset evolution are discussed. In particular, what advances in the radio architecture, for example the zero-IF GSM receiver,the baseband (CMOS) technology, andthe radio system design areasSW-DSP-digital-RF partitioning,linear multi-mode modulation with high linearity requirements,digital leakage issues, andpower consumption limitations in multimedia handsets are discussed with future generation handsets in mind.

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A systemC-based modular design and verification framework for C-model reuse in a HW/SW-codesign design flow

A systemC-based modular design and verification framework fo...

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international conference on Distributed Computing systems Workshop

作者： O. Blaurock Department of Computer Science University of Hamburg Germany

Rising the level of abstraction in system modelling allows early verification of the system functionality, reducing the risk of long redesign cycles. Moving to a new flow introducing systemC as SDL allows the reuse of existing high-level C-models. A framework is presented that allows C-model integration and the connection of modules located at different levels of abstraction without the need to implement the communication or introduce adaptors to translate between the abstraction levels. The focus of the approach lies on high acceptance by the designers coming from a C and HDL based top-down design methodology.

关键词： Design methodology software systems Process design Concurrent computing Electrical equipment industry Industrial control Computer science hardware design languages Time to market Embedded software

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Bluespec system Verilog: efficient, correct RTL from high level specifications

Bluespec System Verilog: efficient, correct RTL from high le...

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ACM and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： R. Nikhil Bluespec Inc. Waltham MA USA

Bluespec system Verilog is an EDL toolset for ASIC and FPGA design offering significantly higher productivity via a radically different approach to high-level synthesis. Many other attempts at high-level synthesis have tried to move the design language towards a more software-like specification of the behavior of the intended hardware. By means of code samples, demonstrations and measured results, we illustrate how Bluespec system Verilog, in an environment familiar to hardware designers, can significantly improve productivity without compromising generated hardware quality.

关键词： hardware Productivity High level synthesis Atomic measurements Application specific integrated circuits Field programmable gate arrays Flow graphs Scheduling Logic design Predictive models

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A modular approach to systemC-based codesign promoting reuse of high-level legacy C-models

A modular approach to systemC-based codesign promoting reuse...

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international conference and Workshop on Engineering of Computer-Based systems

作者： O. Blaurock Dept. of Computer Science University of Hamburg Germany

Today's systems-on-chip have reached a complexity that demands high-level modelling for both design and verification. By raising the level of abstraction and supporting seamlessness in the methodology new design flows increases the productivity. High level models described on the basis of the C/C++ language family are widely used. Introducing a new flow based on the SDL systemC allows reuse of such legacy models. A refinement method and a supporting framework are presented to integrate C-code for software and hardware components into a system level model. The focus of the presentation is on the multilevel model support of the framework.

关键词： conferences systems engineering and theory

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Dynamic reconfiguration of distributed arithmetic controllers: design space exploration and trade-off analysis

Dynamic reconfiguration of distributed arithmetic controller...

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international Symposium on Parallel and Distributed Processing (IPDPS)

作者： K. Danne C. Bobda Heinz Nixdorf Institute University of Paderborn Paderborn Germany Hardware/Software Codesign Institute University of Erlangen Nuremberg Erlangen Germany

Summary form only given. This work explores various solutions to implement an application using runtime reconfigurable field programmable gate arrays (FPGA). The example is a mechatronic control system which has to adapt its behavior from time to time. Our model is a task-graph where every task is associated with an hardware module characterized by its required FPGA resource and its execution time. We propose various mappings of the tasks onto the FPGA. For the implementation of the tasks themselves the computation technique known as distributed arithmetic is used. We achieve numerous alternatives with different resource consumptions and execution times for every task. We estimate these characteristics and compare them to synthesis results. The received values are used to get the characteristics of the over-all system. The results show that the optimal mapping depends on the application timing constrains, on the complexity of the tasks as well as on the reconfiguration speed of the used FPGA.

关键词： Arithmetic Distributed control Space exploration Field programmable gate arrays Runtime Mechatronics Control systems hardware Distributed computing Timing

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Synchronous methodology for designing hardware, software and mixed embedded systems

Synchronous methodology for designing hardware, software and...

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international conference on VLSI Design

作者： G. Berry Esterel Technologies TWINSI Villeneuve Loubet France

The tutorial presents the synchronous methodology for the design of hardware, software, or mixed embedded systems. This methodology was initially developed in the mid 80's in research, with the creation of synchronous languages such as Esterel, Lustre, or Signal. It became industrial in the 90's and is now used in a wide range of applications, from the design of safety-critical systems in avionics or automobile to the design and verification of complex electronic circuits and systems on Chip. We first present the basic cycle-based synchronous computation model and give a general overview of synchronous techniques, tools, and application areas. We explain why the synchronous approach makes design safer and verification simpler and we give industrial references. We then address the following technical issues: textual vs. graphical specification; sequencing, concurrency, and preemption; control path vs. data path; optimized hardware and software synthesis; formal verification of assertions and properties. We illustrate the topics by various examples, using the Esterel Studio system for demos. Finally, we show how synchronous techniques make it possible to generate hardware or software from the same specification and with the very same semantics, and how they fit in conventional hardware and software workflows.

关键词： Design methodology software design hardware Embedded software Embedded system Application software Electronics industry Aerospace electronics Automobiles Electronic circuits

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