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Integrating assertion-based verification into system-level synthesis methodology

Integrating assertion-based verification into system-level s...

引用

international conference on Microelectronics, ICM

作者： S. Hessabi A.M. Gharehbaghi B.H. Yaran M. Goudarzi Department of Computer Engineering Sharif University of Technology Iran Department of Computer Engineering Sharif University of Technology

In this paper, we integrate a verification methodology with our object-oriented system-level synthesis methodology to address the problem of HW/SW co-verification after system synthesis. We have defined a set of system-level assertions. These assertions are automatically converted to monitor hardware or monitor software during the system-level synthesis process depending on their type and also synthesis style of their corresponding functions. The synthesized assertions are functionally equivalent to their original system-level assertion, and hence, can he used to verify the system after HW/SW synthesis. This way, not only system-level assertions are reused in lower-levels of abstraction, but also run-time verification of system is provided. In this paper, we show the system-level assertions and their synthesis method in our object-oriented system-level synthesis methodology.

关键词： hardware Computerized monitoring Object oriented modeling Embedded system Runtime Emulation Reliability Application specific processors Circuit synthesis system-level design

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Reliability-aware co-synthesis for embedded systems

Reliability-aware co-synthesis for embedded systems

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international conference on Application Specific systems (ASAP), Architectures and Processors

作者： Y. Xie L. Li M. Kandemir N. Vijaykrishnan M.J. Irwin Department of Computer Science and Engineering Pennsylvania State University USA Department of Computer Science and Engineering Pennsylvania State University

As technology scales, transient faults due to single event upsets have emerged as a key challenge for reliable embedded system design. This work proposes a design methodology that incorporates reliability into hardware-software co-design paradigm for embedded systems. We introduce an allocation and scheduling algorithm that efficiently handles conditional execution in multi-rate embedded systems, and selectively duplicates critical tasks to detect soft errors, such that the reliability of the system is increased. The increased reliability is achieved by utilizing the otherwise idle computation resources and incurs no resource or performance penalty. The proposed algorithm is fast and efficient, and is suitable for use in the inner loop of our hardware/software co-synthesis framework, where the scheduling routine has to be invoked many times.

关键词： Embedded system hardware Single event upset Costs Scheduling algorithm Aerospace electronics Computer architecture Signal processing algorithms Application software Time to market

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The model design of hardware voter

The model design of hardware voter

引用

international conference on Machine Learning and Cybernetics (ICMLC)

作者： Peng Zhao Qian Zhang Yong Wang Xiutai Yang College of Business Administration Chongqing University Chongqing China College of Electrical Engineering Chongqing University Chongqing China

ISBN: (纸本)0780384032

The voter, as the key component in either multi-model group system in the field of industry control or in the group decision support system, is the guarantee of efficiency of whole work and reliability. In the common situation, the voter can be realized by the pure-software. However, in the comparatives rigid industry-control field, especially in the group control or decision in distance under internet environment, the voter is easy to be interfered by the electromagnetism, even computer virus or hacker program and system has some degree of patient danger. On the other hand, in some situations of high requirement of responsible time, such as instant control system in the electronic net, prediction of short time charge in electronic system and adjustable decision system, software voter model is hard to meet the requirement of system velocity. hardware voter, however, based on the hardware logic model, has much more advantage in the velocity and reliability than software one.

关键词： hardware Electrical equipment industry Industrial control Control systems Computer hacking Decision support systems Computer industry Internet Control system synthesis Velocity control

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CHARMED: a multi-objective co-synthesis framework for multi-mode embedded systems

CHARMED: a multi-objective co-synthesis framework for multi-...

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international conference on Application Specific systems (ASAP), Architectures and Processors

作者： V. Kianzad S.S. Bhattacharyya ECE Department and Institute for Advanced Computer Studies University of Maryland College Park MD USA

We present a modular co-synthesis framework called CHARMED that solves the problem of hardware-software co-synthesis of periodic, multi-mode, distributed, embedded systems. In this framework we perform the synthesis under several constraints while optimizing for a set of objectives. We allow the designer to fully control the performance evaluation process, constraint parameters, and optimization goals. Once the synthesis is performed, we provide the designer a non-dominated set (Pareto front) of implementations on streamlined architectures that are in general heterogeneous and distributed. We also employ two different techniques, namely clustering and parallelization, to reduce the complexity of the solution space and expedite the search. The experimental results demonstrate the effectiveness of the CHARMED framework in computing efficient co-synthesis solutions within a reasonable amount of time.

关键词： Embedded system Constraint optimization Cost function Application software Embedded computing Control system synthesis Design optimization hardware Data communication Optimization methods

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Bluespec system Verilog: efficient, correct RTL from high level specifications 04

Bluespec System Verilog: efficient, correct RTL from high le...

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proceedings of the Second ACM/IEEE international conference on Formal Methods and Models for Co-Design

ISBN: (纸本)9780780385092

Bluespec system Verilog is an EDL toolset for ASIC and FPGA design offering significantly higher productivity via a radically different approach to high-level synthesis. Many other attempts at high-level synthesis have tried to move the design language towards a more software-like specification of the behavior of the intended hardware. By means of code samples, demonstrations and measured results, we illustrate how Bluespec system Verilog, in an environment familiar to hardware designers, can significantly improve productivity without compromising generated hardware quality.

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systemoprh: dynamic/online/adaptive system-level optimization for SoC

SysteMoprh: dynamic/online/adaptive system-level optimizatio...

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international conference on High Performance Computing in the Asia-Pacific Region

作者： N. Yoshimatsu M. Yoshida T. Soga M. Shuto Y. Tanoue Y. Fujii K. Eshima T. Hayashidai K. Murakami Fukuoka Industry Japan Fukuoka Industry Science & Technology Foundation Japan Institute of Systems & Information Technologies/KYUSHU Department of Informatics Kyushu University Japan Department of Informatics Kvushu University

This work describes systemorph, a feedback directed dynamic, online and adaptive hardware/instruction set architecture (JSA)/software co-optimization technology. The technology enables to optimize performance, power, and consumption energy for a system dynamically. We describe systemorphs elemental technologies those are an online profiling, a dynamic adaptive optimization and a smart hardware. Functionality morphing is one of the systemorph implementations for a system which consists of processor and reconfigurable logic. It reconfigures hardware dynamically then rewrites software to utilize the reconfigured hardware online. We demonstrated the systemorph on a reconfigurable processor by implementing functionality morphing. Online profiling, online synthesis, and binary rewriting are implemented and verified on the prototypal system. Then we propose a processor suitable implementing systemorph using a VUW execution unit.

关键词： Adaptive systems hardware Energy consumption Feedback Computer architecture Reconfigurable logic Prototypes VLIW Application software Computer industry

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synthesis-driven exploration of pipelined embedded processors

Synthesis-driven exploration of pipelined embedded processor...

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international conference on VLSI Design

作者： P. Mishra A. Kejariwal N. Dutt Architectures and Compilers for Embedded Systems (ACES) Laboratory Center for Embedded Computer Systems University of California Irvine CA USA

Recent advances on language based software toolkit generation enables performance driven exploration of embedded systems by exploiting the application behavior. There is a need for an automatic generation of hardware to determine the required silicon area, clock frequency, and power consumption of the candidate architectures. In this paper, we present a language based exploration framework that automatically generates synthesizable RTL models for pipelined processors. Our framework allows varied micro-architectural modifications, such as, addition of pipeline stages, pipeline paths, opcodes and new functional units. The generated RTL is synthesized to determine the area, power, and clock frequency of the modified architectures. Our exploration results demonstrate the power of reuse in composing heterogeneous architectures using functional abstraction primitives allowing for a reduction in the time for specification and exploration by at least an order of magnitude.

关键词： Power generation Clocks Pipelines Embedded software software performance software tools Distributed power generation Embedded system Application software hardware

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Application of Squeak/Croquet environment for embedded systems development

Application of Squeak/Croquet environment for embedded syste...

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international conference on Creating, Connecting and Collaborating Through Computing

作者： M. Sakai Y. Ishizaki A. Togawa T. Yamamoto Micronet Company Limited Japan Hokkaido University Japan

Development processes of embedded systems have been discussed many years and there exist number of advanced development environments. A well-designed development system may give us a unified design concept but such environment consists of components provided by a single vender in most case. A mixed-vendor environment can pick up nice feature of each system, however the coherency of concept and operation may be sacrificed. We discuss about unification of design process based on UML methodology. We are developing prototype of Squeak/Croquet based embedded system development environment in which mixed-vender design components are integrated in unified operation style.

关键词： Embedded system Unified modeling language software design Process design Application software Circuit synthesis Communication industry hardware Prototypes Embedded software

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Human figure control software for real-virtual application

Human figure control software for real-virtual application

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international conference on Information Visualisation (IV)

作者： S. Yonemoto R. Taniguchi Department of Information Science Kyushu Sangyo University Fukuoka Japan Department of Intelligent Systems Kyushu University Fukuoka Japan

We present human figure control software using vision-based human motion capturing. We have already developed core techniques for vision-based human motion tracking and motion synthesis. We have provided the first version software as an open source kit. In this work, we have developed the second version software with modified motion synthesis. Our software consists of the following software: the vision software (includes 2D blob tracking modules and stereo vision module) and the motion synthesis software (includes skeletal structure reconstruction from a limit number of 3D positions, i.e., physically simulated joint position estimator). This software can be employed for many real-virtual applications such as avatar based video conferencing, virtual human control, and 3D game consoles which need the user postures as input. Our software requires the following hardware: more than two firewire cameras for vision processing and more than one PC for vision processing, motion synthesis, and rendering. In our real-virtual system, this software is also employed for virtual object manipulation interface with augmented avatar representation.

关键词： Humans Application software Open source software Tracking Avatars Firewire Motion control Stereo vision Joints Motion estimation

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A methodology for timing and structural communication refinement in DSP systems

A methodology for timing and structural communication refine...

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international conference on Microelectronics, ICM

作者： F. Thabet J.-B. Le Goff P. Coussy E. Martin Lester-FRE 2734 University of South Brittany Lorient France

Modern systems become more and more complex and tendency turn to the integration on one single chip: system on chip (SoC). systemC is proposed as a standardized modeling language intended to enable system level design at multiple abstraction levels for hardware/software systems. This paper describes a method of stepwise communication refinement with systemC, starting from an algorithmic description and progressively adding implementation details for both data type and timing constraints. We show the effectiveness of our approach with an experiment based on a discrete cosine transform DCT algorithm.

关键词： Timing Digital signal processing Signal processing algorithms hardware Digital signal processing chips Design methodology Process design Acceleration Signal synthesis Discrete cosine transforms

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