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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1553 条记录，以下是1051-1060 订阅

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A low-cost memory architecture with NAND XIP for mobile embedded systems

A low-cost memory architecture with NAND XIP for mobile embe...

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1st IEEE/ACM/IFIP international conference on Hardward/software codesign and system synthesis

作者： Park, C Seo, J Bae, S Kim, H Kim, S Kim, B Samsung Elect Co Ltd Software Ctr Seoul 135893 South Korea

ISBN: (纸本)1581137427

NAND flash memory has become an indispensable component in mobile embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cost and high density. Even though NAND flash memory is gaining popularity as data storage, it can be also exploited as code memory for XIP (execute-in-place). In this paper, we present a new memory architecture which incorporates NAND flash memory into an existing memory hierarchy for code execution. The usefulness of the proposed approach is demonstrated with real embedded workloads on a real prototyping board.

关键词： memory architecture NAND XIP priority-based caching

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Deriving process networks from weakly dynamic applications in system-level design

Deriving process networks from weakly dynamic applications i...

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1st IEEE/ACM/IFIP international conference on Hardward/software codesign and system synthesis

作者： Stefanov, T Deprettere, E Leiden Univ Leiden Inst Adv Comp Sci Leiden Embedded Res Ctr NL-2300 RA Leiden Netherlands

ISBN: (纸本)1581137427

We present an approach to the automatic derivation of executable Process Network specifications from Weakly Dynamic Applications. We introduce the notions of Dynamic Single Assignment Code, Approximated Dependence Graph, and Linearly Bounded Sets to model and capture weakly dynamic (data-dependent) behavior of applications at the task-level of abstraction. Process Networks are simple parallel processing models that match the emerging multi-processor architectures in the sense that the mapping of Process Network specifications of applications onto multi-processor architectures can be done in a systematic and transparent way.

关键词： system-level design heterogeneous embedded systems kahn process networks weakly dynamic applications

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Dynamic hardware/software partitioning: A first approach

Dynamic hardware/software partitioning: A first approach

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40th Design Automation conference

作者： Stitt, G Lysecky, R Vahid, F Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)1581136889

Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy consumption in embedded systems. Meanwhile, dynamic software optimization methods have shown the usefulness and feasibility of runtime program optimization, but those optimizations do not. achieve as much as partitioning. We introduce a first approach to dynamic hardware/software partitioning. We describe our system architecture and initial on-chip tools, including profiler, decompiler, synthesis, and placement and routing tools for a simplified configurable logic fabric, able to perform dynamic partitioning of real benchmarks. We show speedups averaging 2.6 for five benchmarks taken from Powerstone, NetBench, and our own benchmarks.

关键词： hardware/software partitioning FPGA synthesis platforms system-on-a-chip dynamic optimization codesign self-improving chips embedded systems

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Synthesizing operating system based device drivers in embedded systems

Synthesizing operating system based device drivers in embedd...

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1st IEEE/ACM/IFIP international conference on Hardward/software codesign and system synthesis

作者： Wang, SJ Malik, S Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)1581137427

This paper presents a correct-by-construction synthesis method for generating operating system based device drivers from a formally specified device behavior model. Existing driver development is largely manual using an ad-hoc design methodology. Consequently, this task is error prone and becomes a bottleneck in embedded system design methodology. Our solution to this problem starts by accurately specifying device access behavior with a formal model, viz. extended event driven finite state machines. We state easy to check soundness conditions on the model that subsequently guarantee properties such as bounded execution time and deadlock-free behavior. We design a deadlock-free resource accessing scheme for our device access model. Finally, we synthesize an operating system (OS) based event processing mechanism, which is the core of the device driver, using a disciplined methodology that assures the correctness of the resulting driver. We validate our synthesis method using two case studies: an infrared port and the USB device controller for an SA I 100 based handheld. Besides assuring a correct-by -construction driver, the size of the specification is 70% smaller than a manually written driver, which is a strong indicator of improved design productivity.

关键词： correct-by-construction device driver operating system based software synthesis embedded system software

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SEAS: A system for early analysis of SoCs

SEAS: A system for early analysis of SoCs

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1st IEEE/ACM/IFIP international conference on Hardward/software codesign and system synthesis

作者： Bergamaschi, RA Shin, YS Dhanwada, N Bhattacharya, S Dougherty, WE Nair, I Darringer, J Paliwal, S IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

ISBN: (纸本)1581137427

systems-on-chip (SoC) continue to be very complex to design and verify, despite extensive component reuse. Although reusable components are pre-designed and pre-verified, when they are assembled in an SoC there is no guarantee that the whole system will behave as expected from a performance, cost and integration point of view. In many cases this is because of faulty early design decisions regarding the architecture, core selection, floorplanning, etc. This paper presents a system for early analysis of SoCs which helps designers make early design decisions regarding performance, area, timing and power;and allows them to quickly evaluate cross-domain effects, such as the effect that an architectural decision may have on the performance and chip area.

关键词： design analysis design space exploration performance power floorplanning

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Design Space Exploration of a hardware-software Co-designed GF(2 m) Galois Field Processor for Forward Error Correction and Cryptography 03

Design Space Exploration of a Hardware-Software Co-designed ...

引用

First IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2003

作者： Lim, Wei-Ming Benaissa, M. University of Sheffield Department of Electronic Engineering Mappin Street Sheffield S1 3JD United Kingdom

ISBN: (纸本)9781581137422

This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m), such as RS and BCH codes, Elliptic Curve Cryptography and the AES. Complexities of flexible implementations of different applications on a same computation architecture can be migrated to software during design time. However, the underlying GF(2m) arithmetic architecture needs to be designed with software programmability (or reconfigurability) in mind. We describe novel reconfigurable subword parallel GF(2m) arithmetic architectures designed with an associated instruction set architecture for different applications over GF(2m) and same applications with differing parameters. Design space exploration is carried out with two simple parameters P and Q which can be changed at design time and will affect the performance of different applications and flexibility of the final implementation. We show implementation results given for an FPGA prototype of the processor and programmed for RS and BCH coding, AES and elliptic curve cryptography with differing parameters. Complexity figures and configuration overheads for subword parallel GF(2m) arithmetic architectures are also estimated and discussed.

关键词： Program processors

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Interface design approach for system on chip based on configuration

Interface design approach for system on chip based on config...

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proceedings of the 2003 IEEE international Symposium on Circuits and systems

作者： Maalej, Issam Gogniat, Guy Abid, Mohamed Philippe, Jean Luc ENIS Dept. de Génie Élec. B.P: W 3038 Sfax Tunisia L.E.S.T.E.R. Université de Bretagne Sud Rue Saint Maude 56100 Lorient France

Communication synthesis is an essential step in hardware/software co-synthesis: many embedded systems use automatic generation of interface for point to point communication or use external supports of communication as standard bus or micro network. In this paper, we address the problem of hardware - software interface design in codesign approach for real-time applications. We refer to the hardware component as hardware accelerator and the software component as processor. In our approach, the accelerators are directly integrated into the processor core in order to optimize the transfers of data between the two units. In this paper we describe a configuration approach to design a communication interface.

关键词： Telecommunication systems

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From use cases to system implementation: Statechart based co-design 1

From use cases to system implementation: Statechart based co...

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1st ACM/IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE 03)

作者： Gomes, L Costa, A Univ Nova Lisboa Fac Ciencias & Tecnol Dept Elect Engn P-2825 Monte De Caparica Portugal

ISBN: (纸本)0769519237

This paper proposes a methodology for embedded systems co-design, based on statechart models. The process starts with grabbing the system functionalities through use cases. A set of procedures addressing the implementation of Statechart models is presented. The main goal of this set of procedures is to lift the structuring mechanisms presented in statecharts to the top level. In this sense, the complexity of statechart implementation will be similar to the complexity of communicating concurrent state machines and the platforms selected to support implementation will not need to have specific capabilities to directly support the structuring mechanisms of Harel's statecharts. As a consequence, full direct implementation of statecharts is possible considering different types of implementation platforms, ranging from hardware-centric or software-centric to hardware-software partitioning through codesign techniques.

关键词： Computational modeling Computer aided software engineering Concurrent computing Data processing Embedded computing Embedded software Embedded system hardware Real time systems Unified modeling language

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SoC synthesis with automatic hardware software interface generation 16

SoC synthesis with automatic hardware software interface gen...

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16th international conference on VLSI Design/2nd international conference on Embedded systems Design

作者： Singh, A Chhabra, A Gangwar, A Dwivedi, BK Balakrishnan, M Kumar, A Tejas Networks Bangalore Karnataka India

ISBN: (纸本)0769518680

Design of efficient system-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardware in order to meet the cost as well as the performance constraints. However, faster time to market requires automation of synthesis of these code segments of the application from high level specification such as C alongwith its interfaces. Such synthesis system should be able to generate hardware which is easily plug-gable in various types of architectures, as well as augment the application code to automatically take advantage of this new hardware component. In this paper we address this problem and present an approach for complete SoC synthesis. We automatically generate synthesizable VHDL for the compute intensive part of the application alongwith necessary interfaces. Our approach is generic in the sense that it supports various processors and buses by keeping a generic hardware interface on one end and a dedicated one on the other The generated hardware can be used in a tightly or loosely coupled manner in terms of memory and register communication. We present the effectiveness of this approach for some commonly used image processing. spatial filter applications.

关键词： Automation Computer architecture Computer interfaces Costs hardware Image processing Registers Spatial filters system-on-a-chip Time to market

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Interface synthesis using memory mapping for an FPGA platform

Interface synthesis using memory mapping for an FPGA platfor...

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21st international conference on Computer Design

作者： Luthra, M Gupta, S Dutt, N Gupta, R Nicolau, A Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92717 USA

ISBN: (纸本)0769520251

Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) as a programmable co-processor to reduce the computational load on the main processor core. In this paper we present an interface synthesis approach that forms part of our hardware-software co-design methodology for such an FPGA-based platform. The approach is based on a novel memory mapping algorithm that maps data used by both the hardware and the software to shared memories on the reconfigurable fabric. The memory mapping algorithm couples with a high-level synthesis tool and uses scheduling information to map variables, arrays and complex data structures to the shared memories in a way that minimizes the number of registers and multiplexers used in the hardware interface. We also present three software schemes that enable the application software to communicate with this hardware interface. We demonstrate the utility of our approach and study the trade-offs involved using a case study of the co-design of a computationally expensive portion of the MPEG-1 multimedia application on to the Altera Nios platform.

关键词： Integrated circuit layout

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