We describe a three-course upper-division undergraduate sequence at the University of California, Riverside that teaches both the principles and the practice of embedded system design. While many courses teach embedde...
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ISBN:
(纸本)0769519733
We describe a three-course upper-division undergraduate sequence at the University of California, Riverside that teaches both the principles and the practice of embedded system design. While many courses teach embedded systems programming, typically at the assembly language level, few teach the principles of the field - especially with respect to hardware and softwarecodesign. The courses have been under development since 1994 and have been quite stable for several years. The courses are based on a new textbook that emphasizes a unified view of hardware and software. All three courses include both lectures and an extensive lab component. Feedback from students who have graduated and work in the embedded systems field has been excellent.
Consumer demand and improvements in hardware have caused distributed real-time embedded systems to rapidly increase in complexity. As a result, designers faced with time-to-market constraints are forced to rely on int...
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ISBN:
(纸本)0769518680
Consumer demand and improvements in hardware have caused distributed real-time embedded systems to rapidly increase in complexity. As a result, designers faced with time-to-market constraints are forced to rely on intelligent design tools to enable them to keep up with demand These tools are continually being used earlier in the design process when the design is at higher levels of abstraction. At the highest level of abstraction are hardware/software co-synthesis tools which take a system specification as input. Although many embedded systems are described in C, the system specifications for many of these tools are often in the form of one or more task graphs. These tools are very effective at solving the co-synthesis problem using task graphs but require that designers manually transform the specification from C code to task graphs, a tedious and error-prone job. The task graph extraction tool described in this paper reduces the potential for error and the time required to design an embedded system by automating the task graph extraction process. Such a tool can drastically improve designer productivity. As far as we know, this is the first tool of its kind. It has been made available on the web.
CAD vendors are always faced with the question of what tools to develop and how much can they charge for them. Designers on the other hand have real problems to solve and before investing in tools they have to assess ...
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ISBN:
(纸本)1581137427
CAD vendors are always faced with the question of what tools to develop and how much can they charge for them. Designers on the other hand have real problems to solve and before investing in tools they have to assess how much a given tool will actually save them. CAD vendors and designers have to estimate the savings in design time and cost that a tool may provide and compare that with the existing way of doing things, to determine if the investment in tool creation is justified. For example, if a misguided architectural decision causes weeks of delay because of missing performance targets, then a tool for early architectural analysis may be very valuable. system-level design poses exactly these types of questions because it involves optimizations and analyses across many domains, from software, to architecture, to cycle-time, and is done very early in the design cycle where it has a profound impact. How much improvement in productivity and overall design quality (e.g., timing, area, and power) can be attained by current and future generations of system-level tools? If designers believe such improvements can be obtained, are they prepared to pay the appropriate price for the tools? Or do system-level CAD vendors still need to make believers out of designers? This panel will bring together industry experts to review the current and future industry needs for system-level design technologies as well as discuss how much saving in design time and cost such tools can hope to achieve and whether the designers believe the price is right for the return they can get.
The main goal of this project is to provide a method of correct design of digital circuit. It combines the advantages of VHDL, the well-known language of circuit design, with the Power of B method that guarantees the ...
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ISBN:
(纸本)0769518877
The main goal of this project is to provide a method of correct design of digital circuit. It combines the advantages of VHDL, the well-known language of circuit design, with the Power of B method that guarantees the correct design (w.r.t. a formal specification). This allows avoiding the design test since it is "correct by proven construction". Furthermore, this project provides a tool, called BHDL, with a graphical interface for creating, editing, viewing and proving modular hardware architectures.
The following topics are dealt with: hardware-softwarecodesign; systemsynthesis; architectural exploration; system simulation; system modeling; real time services; OS services; embedded software; embedded hardware; ...
The following topics are dealt with: hardware-softwarecodesign; systemsynthesis; architectural exploration; system simulation; system modeling; real time services; OS services; embedded software; embedded hardware; on-chip communication; scheduling techniques; system verification; system analysis; system design; performance evaluation; and compiler optimizations.
Heuristics for reconstructing the phylogenetic tree of DNA sequences based on maximum likelihood are computationally expensive. The tree evaluation function that calculates the likelihood value for each tree topology ...
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ISBN:
(纸本)0769520006
Heuristics for reconstructing the phylogenetic tree of DNA sequences based on maximum likelihood are computationally expensive. The tree evaluation function that calculates the likelihood value for each tree topology dominates the time in searching the optimal tree. We developed a hybrid hardware/software (HW/SW) system for solving the phylogenetic tree reconstruction problem using the Genetic Algorithm for Maximum Likelihood (GAML) approach. The GAML is partitioned into a genetic algorithm (GA) and a fitness evaluation function, with the SW handling the GA and the HW evaluating the maximum likelihood function. This approach exploits the flexibility of software and the speed up of high performance hardware. An efficient Field Programmable Gate Arrays (FPGA) implementation for the required computation on evolution tree topology fitness evaluation is proposed The complete high-level digital design is developed and Xilinx's Java-based JBits toolkit is used for constructing a BRAM interface for digital process synchronization control and GA chromosomes transmission between a workstation and the Xilinx Virtex-800 FPGA Processor. This implementation provides approximately 30 to 100 times in speedup improvement when compared to a software solution.
CSP (Communicating Sequential Processes) is a useful algebraic notation for creating a hierarchical behavioural specification for concurrent systems, due to its formal interprocess synchronization and communication se...
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ISBN:
(纸本)0769519237
CSP (Communicating Sequential Processes) is a useful algebraic notation for creating a hierarchical behavioural specification for concurrent systems, due to its formal interprocess synchronization and communication semantics. CSP specifications are amenable to simulation and formal verification by model-checking tools. To overcome the drawback that CSP is neither a full-featured nor popular programming language, an approach called "selective formalism" allows the use of CSP to be limited to specifying the control portion of a system, while the rest of its functionality is supplied in the form of C++ modules. These are activated through association with abstract events in the CSP specification. The target system is constructed using a framework called CSP++, which automatically translates CSP specifications into C++, thereby making CSP directly executable. Thus a bridge is built that allows a formal method to be combined with a popular programming language. It is believed that this methodology can be extended to hardware/softwarecodesign.
This paper presents a new method for implementing in hardware expert systems based on belief revision concepts. The expert system's knowledge base is first automatically translated to an equivalent network represe...
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ISBN:
(纸本)3540408223
This paper presents a new method for implementing in hardware expert systems based on belief revision concepts. The expert system's knowledge base is first automatically translated to an equivalent network representation where nodes are facts and links stand for relationships. Then, changes are propagated throughout the network. The conclusions are extracted after no more changes occur in the state of the nodes. The automatic generation of the hardware network structure is described. Finally, the results obtained in this FPGA-based implementation are compared to those yielded by a Java-based implementation, the system's efficiency being thus demonstrated.
This paper describes the combination of educating both, hardware and software with one practical lab. The needs to offer such a co-training concept are brought out by the demands of industry towards the desired skills...
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ISBN:
(纸本)0769519733
This paper describes the combination of educating both, hardware and software with one practical lab. The needs to offer such a co-training concept are brought out by the demands of industry towards the desired skills of today's engineers. An engineer's view must no longer be restricted to his/her own work, but has to be widened to a complete system view. To provide an appropriate education scheme the university courses have to adapt to these changes. Therefore an innovative lab concept is presented here. Its goal is to improve students skills not only in a single direction, but to deliver an efficient inter disciplinary hardware/software lab course, combined with training state-of-the-art industrial architectures and relevant tools.
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