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Task graph extraction for embedded system synthesis

Task graph extraction for embedded system synthesis

引用

international conference on VLSI Design

作者： K.S. Vallerio N.K. Jha Department of Electrical Engineering Princeton University Princeton NJ USA

Consumer demand and improvements in hardware have caused distributed real-time embedded systems to rapidly increase in complexity. As a result, designers faced with time-to-market constraints are forced to rely on intelligent design tools to enable them to keep up with demand. These tools are continually being used earlier in the design process when the design is at higher levels of abstraction. At the highest level of abstraction are hardware/software co-synthesis tools which take a system specification as input. Although many embedded systems are described in C, the system specifications for many of these tools are often in the form of one or more task graphs. These tools are very effective at solving the co-synthesis problem using task graphs but require that designers manually transform the specification from C code to task graphs, a tedious and error-prone job. The task graph extraction tool described in this paper reduces the potential for error and the time required to design an embedded system by automating the task graph extraction process. Such a tool can drastically improve designer productivity. As far as we know, this is the first tool of its kind. It has been made available on the web.

关键词： Embedded system hardware software libraries Real time systems software tools Embedded software Process design Productivity Field programmable gate arrays Job design

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SEAS: a system for early analysis of SoCs 03

SEAS: a system for early analysis of SoCs

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proceedings of the 1st IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Reinaldo A. Bergamaschi Youngsoo Shin Nagu Dhanwada Subhrajit Bhattacharya William E. Dougherty Indira Nair John Darringer Sarala Paliwal IBM T.J. Watson Research Center Yorktown Heights NY IBM EDA Laboratory Fishkill NY

ISBN: (纸本)9781581137422

systems-on-chip (SoC) continue to be very complex to design and verify, despite extensive component reuse. Although reusable components are pre-designed and pre-verified, when they are assembled in an SoC there is no guarantee that the whole system will behave as expected from a performance, cost and integration point of view. In many cases this is because of faulty early design decisions regarding the architecture, core selection, floorplanning, etc. This paper presents a system for early analysis of SoCs which helps designers make early design decisions regarding performance, area, timing and power; and allows them to quickly evaluate cross-domain effects, such as the effect that an architectural decision may have on the performance and chip area.

关键词： design analysis floorplanning design space exploration power performance

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Formal behavioural synthesis of Handel-C parallel hardware implementations from functional specifications

Formal behavioural synthesis of Handel-C parallel hardware i...

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Annual Hawaii international conference on system Sciences (HICSS)

作者： A.E. Abdallah J. Hawkins South Bank University London UK

Enormous improvements in efficiency can be achieved through exploiting parallelism and realizing implementation in hardware. On the other hand, conventional methods for achieving these improvements are traditionally costly, complex and error prone. Two significant advances in the past decade have radically changed these perceptions. Firstly, the FPGA, which gives us the ability to reconfigure hardware through software, dramatically reducing the costs of developing hardware implementations. Secondly, the language Handel-C with primitive explicit parallelism which can compile programs down to an FPGA. In this paper, we build on these recent technological advances and present a systematic approach of behavioural synthesis. Starting with an intuitive high level functional specification of a problem, given without annotation of parallelism, the approach aims at deriving an efficient parallel implementation in Handel-C, which is subsequently compiled into a circuit implemented on reconfigurable hardware. Algebraic laws are systematically used for exposing implicit parallelism and transforming the specification into a collection of interacting components. Formal methods based on data refinement and a small library of higher order functions are then used to derive behavioural description in Handel-C of each component. A small case study illustrates the use of this approach.

关键词： hardware Field programmable gate arrays Costs Algorithm design and analysis Circuit synthesis Application software High level languages Programming profession Art Functional programming

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From algorithm graph specification to automatic synthesis of FPGA circuit: a seamless flow of graphs transformations

From algorithm graph specification to automatic synthesis of...

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13th international conference on Field-Programmable Logic and Applications (FPL 2003)

作者： Kaouane, L Akil, M Sorel, Y Grandpierre, T Lab A2SI Grp ESIEE F-93162 Noisy Le Grand France Inst Natl Rech Informat & Automat OSTRE F-78153 Le Chesnay France

ISBN: (纸本)3540408223

The control, signal and image processing applications are complex in terms of algorithms, hardware architectures and real-time/embedded constraints. system level CAD softwares are then useful to help the designer for prototyping and optimizing such applications. These tools axe oftently based on design flow methodologies. This paper presents a seamless design flow which transforms a data dependence graph specifying the application into an implementation graph containing both data and control paths. The proposed approach follows a set of rules based on the RTL model and on mechanisms of synchronized data transfers in order to transform automatically the initial algorithmic graph into the implementation graph. This transformation flow is part of the extension of our AAA (Algorithm-Architecture Adequation) rapid prototyping methodology to support the optimized implementation of real-time applications on reconfigurable circuits. It has been implemented in SynDEx(1), a system level CAD software tool that supports AAA.

关键词： Field programmable gate arrays (FPGA)

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hardware/software co-training by FPGA/ASIC synthesis and programming of a RISC microprocessor-core

Hardware/software co-training by FPGA/ASIC synthesis and pro...

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IEEE international conference on Microelectronic systems Education

作者： J.E. Becker C. Bieser A. Thomas K.D. Muller-Glaser J. Becker Institut für Technik der Informationsverarbeitung Universität Karlsruhe Germany

ISBN: (纸本)0769519733

This paper describes the combination of educating both, hardware and software with one practical lab. The needs to offer such a co-training concept are brought out by the demands of industry towards the desired skills of today's engineers. An engineer's view must no longer be restricted to his/her own work, but has to be widened to a complete system view. To provide an appropriate education scheme the university courses have to adapt to these changes. Therefore an innovative lab concept is presented here. Its goal is to improve students skills not only in a single direction, but to deliver an efficient inter disciplinary hardware software lab course, combined with training state-of-the-art industrial architectures and relevant tools.

关键词： hardware Field programmable gate arrays Application specific integrated circuits Reduced instruction set computing software design Programming profession Industrial training Computer industry Electronic mail software tools

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SoC synthesis with automatic hardware-software interface generation

SoC synthesis with automatic hardware-software interface gen...

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international conference on VLSI Design

作者： A. Singh A. Chhabra A. Gangwar B.K. Dwivedi M. Balakrishnan A. Kumar Tejas Networks India Private Limited Bangalore India STMicroelectronics Private Limited Noida India Department of Computer Science & Engineering Indian Institute of Technology New Delhi India

Design of efficient system-on-chips (SoCs) requires thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardware in order to meet the cost as well as the performance constraints. However, faster time to market requires automation of synthesis of these code segments of the application from high level specification such as C along with its interfaces. Such a synthesis system should be able to generate hardware which is easily pluggable in various types of architectures, as well as augment the application code to automatically take advantage of this new hardware component. In this paper, we address this problem and present an approach for complete SoC synthesis. We automatically generate synthesizable VHDL for the compute intensive part of the application along with necessary interfaces. Our approach is generic in the sense that it supports various processors and buses by keeping a generic hardware interface on one end and a dedicated one on the other. The generated hardware can be used in a tightly or loosely coupled manner in terms of memory and register communication. We present the effectiveness of this approach for some commonly used image processing spatial filter applications.

关键词： hardware system-on-a-chip Costs Time to market Automation Computer architecture Computer interfaces Registers Image processing Spatial filters

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Bridging CSP and C++ with selective formalism and executable specifications 03

Bridging CSP and C++ with selective formalism and executable...

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ACM and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： W.B. Gardner Department of Computing & Information Science University of Guelph Guelph ONT Canada

ISBN: (纸本)9780769519234

CSP (communicating sequential processes) is a useful algebraic notation for creating a hierarchical behavioral specification for concurrent systems, due to its formal interprocess synchronization and communication semantics. CSP specifications are amenable to simulation and formal verification by model-checking tools. To overcome the drawback that CSP is neither a full-featured nor popular programming language, an approach called "selective formalism" allows the use of CSP to be limited to specifying the control portion of a system, while the rest of its functionality is supplied in the form of C++ modules. These are activated through association with abstract events in the CSP specification. The target system is constructed using a framework called CSP++, which automatically translates CSP specifications into C++, thereby making CSP directly executable. Thus a bridge is built that allows a formal method to be combined with a popular programming language. It is believed that this methodology can be extended to hardware/software codesign.

关键词： Computer languages hardware Communication system control Automatic control Spine Concurrent computing Information science Computational modeling Formal verification Control systems

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BHDL: circuit design in B

BHDL: circuit design in B

引用

international conference on Application of Concurrency to system Design

作者： A. Aljer P. Devienne S. Tison J.-L. Boulanger G. Mariano Laboratoire d'Informatique Fondamentale de Lille France Heudiasyc Université de Compiagne France Institut National de Recherche sur les Transports et leur Sécurité France

The main goal of this project is to provide a method of correct design of digital circuit. It combines the advantages of VHDL, the well-known language of circuit design, with the power of B method that guarantees the correct design (w.r.t. a formal specification). This allows avoiding the design test since it is "correct by proven construction". Furthermore, this project provides a tool, called BHDL, with a graphical interface for creating, editing, viewing and proving modular hardware architectures.

关键词： Circuit synthesis hardware Digital circuits Formal specifications Design methodology Circuit testing Circuit simulation software tools software prototyping Computer languages

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system-level design tools: who needs them, who has them, and how much should they cost? 03

System-level design tools: who needs them, who has them, and...

引用

proceedings of the 1st IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Reinaldo Bergamaschi Grant Martin IBM Yorktown Heights NY Cadence Berkeley Labs Berkeley CA

ISBN: (纸本)9781581137422

CAD vendors are always faced with the question of what tools to develop and how much can they charge for them. Designers on the other hand have real problems to solve and before investing in tools they have to assess how much a given tool will actually save them. CAD vendors and designers have to estimate the savings in design time and cost that a tool may provide and compare that with the existing way of doing things, to determine if the investment in tool creation is justified. For example, if a misguided architectural decision causes weeks of delay because of missing performance targets, then a tool for early architectural analysis may be very valuable. system-level design poses exactly these types of questions because it involves optimizations and analyses across many domains, from software, to architecture, to cycle-time, and is done very early in the design cycle where it has a profound *** much improvement in productivity and overall design quality (e.g., timing, area, and power) can be attained by current and future generations of system-level tools? If designers believe such improvements can be obtained, are they prepared to pay the appropriate price for the tools? Or do system-level CAD vendors still need to make believers out of designers?This panel will bring together industry experts to review the current and future industry needs for system-level design technologies as well as discuss how much saving in design time and cost such tools can hope to achieve and whether the designers believe the price is right for the return they can get.

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A model of autonomous control system for deep space missions

A model of autonomous control system for deep space missions

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international conference on Recent Advances in Space Technologies (RAST)

作者： P.L. Hristov P.S. Angelov Space Research Institute Bulgarian Academy of Sciences Sofia Bulgaria

The particularities of autonomous control system for deep space missions are described. Some models are analyzed and compared. The team approach is analyzed in details. The general formal model is based on the theory of communicating sequential processes (CSP) and is set of communicating processes. Methods for reconfiguration, verification and trace control are described.

关键词： Control system synthesis Space missions Space technology Control systems Artificial intelligence Process control Real time systems hardware software systems Runtime

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