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Model-integrated design toolset for polymorphous computer-based systems

Model-integrated design toolset for polymorphous computer-ba...

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international conference and Workshop on Engineering of Computer-Based systems

作者： B. Eames T. Bapty B. Abbott S. Neema K. Chhokra Vanderbilt University USA Southwest Research Institute USA

Polymorphous computer-based systems are systems in which the CPU architecture "morphs" or changes shape to meet the requirements of the application. Optimized and efficient design for these systems requires exploration along axes beyond those of traditional system design. In this paper we outline a model-integrated toolset to aid in the specification, analysis and synthesis of polymorphous applications. Polymorphous systems can be developed utilizing a four-tiered approach, where inherent application properties and characteristics govern design practices at each level. We show through the development of the model-integrated approach that polymorphous system design is inherently coupled with the search and exploration of a combinatorial space of design tradeoffs. Design tools are needed to efficiently evaluate this large and complex space in order to arrive at near-optimal application implementations.

关键词： Computer architecture hardware Application software Embedded system Shape system analysis and design Embedded computing VLIW Space technology Central Processing Unit

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Polychrony for formal refinement-checking in a system-level design methodology

Polychrony for formal refinement-checking in a system-level ...

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international conference on Application of Concurrency to system Design

作者： J.-P. Talpin P. Le Guernic Sandeep Kumar Shukla Rajesh Gupta F. Doucet IRISA INRIA France Virginia Polytechnic Institute and State University USA University of California San Diego USA

The productivity gap incurred by the rising complexity of system-on-chip design have necessitated newer design paradigms to be introduced based on system-level design languages. A gating factors for widespread adoption of these new paradigms is a lack of formal tool support of refinement based design. A system level representation may be refined manually (in absence of adequate behavioral synthesis algorithms and tools) to obtain an implementation, but proving that the lower level representation preserves the correctness proved at higher level models is still an unsolved problem. We address the issue of formal refinement proofs between design abstraction levels using the concepts of polychronous design. Refinement of synchronous high-level designs into globally asynchronous and locally synchronous architectures is formally supported in this methodology. The polychronous (i.e. multiclocked) model of the SIGNAL design language offers formal support for the capture of behavioral abstractions for both very high-level system descriptions (e.g. systemC/SPEcC,) and behavioral-level IP components (e.g. VHDL). Its platform, polychrony, provides models and methods for a rapid, refinement-based, integration and a formal conformance-checking of GALS hardware/software architectures. We demonstrate the effectiveness of our approach by the experimental, comparative, case study of an even-parity checker design in SPEcC. It highlights the benefits of the formal models, methods and tools provided in polychrony, in representing functional, architectural, communication and implementation abstractions of the design, and the successive refinements.

关键词： system-level design Concurrent computing

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codesign-extended applications

Codesign-extended applications

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10th international Symposium on hardware/software codesign (CODES 2002)

作者： Grattan, B Stitt, G Vahid, F Univ Calif Riverside Dept Elect Engn Riverside CA 92521 USA

ISBN: (纸本)1581135424

We challenge the widespread assumption that an embedded system's functionality can be captured in a single specification and then partitioned among software and custom hardware processors. The specification of some functions in software is very different from the specification of the same function in hardware- too different to conceive of automatically deriving one from the other. We illustrate this concept using a digital camera example. We introduce the idea of codesign-extended applications to deal with the situation, wherein critical functions are written in multiple versions, and integrated such that simple compiler/synthesis flags instantiate a particular version along with the necessary control and communication behavior. By capturing a specification as a codesign-extended application, a designer enables smooth migration among platforms with increasing amounts of on-chip configurable logic.

关键词： hardware/software partitioning hardware/software cospecification configurable logic system-on-a-chip platform-based design

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Optimization and synthesis for complex reactive embedded systems by incremental collapsing 02

Optimization and synthesis for complex reactive embedded sys...

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10th international Symposium on hardware/software codesign (CODES 2002)

作者： Chiodo, M Cadence Technol San Jose CA 95134 USA

ISBN: (纸本)1581135424

We propose a software synthesis procedure for reactive real-time embedded systems. In our approach, control parts of the system are represented in a decomposed form enabling more complex control structures to be represented. We propose a synthesis procedure for this representation that incrementally aggregates elements of the representation while keeping the resulting code size under tight control. This method combined with heuristic strategies works very well on real-life designs and demonstrates the potential to produce results that challenge or beat hand-written implementations.

关键词： software synthesis finite-state machines embedded systems real-time systems

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Datapath oriented codesign method of application specific dsps using retargetable compiler

Datapath oriented codesign method of application specific ds...

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Asia-Pacific conference on Circuits and systems

作者： Ishiura, N Watanabe, T Kwansei Gakuin Univ Sch Sci & Technol Sanda Hyogo 6691337 Japan

ISBN: (纸本)0780376900

In this paper, we propose a "datapath oriented" codesign methodology, which uses datapath configurations and horizontal codes, instead of instruction set specifications as an interface between hardware and software. Given an application program and a DSP datapath configuration, the control part of the DSP is synthesized and a horizontal code to control the DSP is generated by a retargetable compiler. This method simplifies the processor synthesis and code generation tasks and will expedite the design automation of application specific DSPs with sophisticated datapaths.

关键词： Application software Automatic generation control Control system synthesis Design automation Design methodology Digital signal processing Digital systems hardware Program processors Signal synthesis

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proceedings of the Tenth international Symposium on hardware/software codesign: CODES 2002

Proceedings of the Tenth International Symposium on Hardware...

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proceedings of the Tenth international Symposium on hardware/software codesign: CODES 2002

The proceedings contains 36 papers. Topics discussed include advances in system identification and system design framework, system design methods, design space exploration and architectural design , co-design architecture and synthesis, system partitioning and timing analysis, energy efficiency in system design and scheduling in systems design.

关键词： systems analysis

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A hierarchical CDFG as intermediate representation for hardware/software codesign 1

A hierarchical CDFG as intermediate representation for hardw...

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international conference on Communications, Circuits and systems

作者： Wu, Q Wang, YF Bian, JN Wu, WM Xue, HX Tsinghua Univ Dept Comp Sci & Technol Beijing 100084 Peoples R China

ISBN: (纸本)0780375475

A hierarchical CDFG model designed as an intermediate representation for hardware/software (HW/SW) codesign is presented in this paper. A new concept of transport node, which represents the communication resources of the system, is proposed in this model. Hierarchical feature can be straightly obtained through extending the definition of nodes, allowing them to nest sub-CDFG recursively. Then it is demonstrated how to build basic control constructs of branches and loops. Explaining in a short introduction to the translation process, such a hierarchical CDFG is suitable for HW/SW codesign as an intermediate representation. The hierarchical CDFG model can capture the design information from source file specified by VHDL or C language. It maintains relative simplicity while providing helpful features for HW/SW partitioning and High-level synthesis tools.

关键词： CDFG (control data flow graph) HW/SW co-design HW/SW partitioning

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Automated systemC to VHDL translation in hardware/software codesign

Automated SystemC to VHDL translation in hardware/software c...

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9th IEEE international conference on Electronics, Circuits and systems

作者： Côtè, C Zilic, Z Teradyne Inc Ind Consumer Div Boston MA USA

ISBN: (纸本)0780375963

Recent advances in electronic circuit technology have enabled the creation of "system-on-chip", which comprise both hardware and software components. codesign takes advantage of this opportunity by considering both components as a whole throughout the design process. While an increasing number of tools are being offered, most concentrate on the simulation of systems, with little or no support for their implementation. This paper describes a translation algorithm developed to act as a bridge between simulation and implementation by translating systemC code to VHDL.

关键词： system-on-chip

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Prototyping of embedded digital systems from SDL language: A case study

Prototyping of embedded digital systems from SDL language: A...

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7th Annual IEEE international Workshop on High-Level Design Validation and Test

作者： Marcon, CAM Hessel, F Amory, AM Ries, LHL Moraes, FG Calazans, NLV

ISBN: (纸本)0780376552

The goal of this paper is to evaluate the performance of embedded digital systems generated from a system level description language. The target language is SDL, which is automatically synthesized with a codesign tool, resulting in VHDL and C descriptions. The codesign tool is responsible for software, hardware and communication synthesis. Two case studies are presented, exploring area and delay results. The results concern only the hardware synthesis, since the goal is to. compare the performance of systems generated from hand coded HDL descriptions against a synthesized HDL. The analysis of the advantages and drawbacks of this automatic. hardware design flow and the evaluation of the commercial tools integration are also reported.

关键词： software prototyping

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hardware/software partitioning of software binaries 02

Hardware/software partitioning of software binaries

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international conference on Computer-Aided Design

作者： Stitt, G Vahid, F Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)0780376072

Partitioning an embedded system application among a microprocessor and custom hardware has been shown to improve the performance, power or energy of numerous examples. The advent of single-chip microprocessor/FPGA platforms makes such partitioning even more attractive. Previous partitioning approaches have partitioned sequential program source code, such as C or C++. We introduce a new approach that partitions at the software binary level. Although source code partitioning is preferable from a purely technical viewpoint, binary-level partitioning provides several very practical benefits for commercial acceptance. We demonstrate that binary-level partitioning yields competitive speedup results compared to source-level partitioning, achieving an average speedup of 1.4 compared to 1.5 for eight benchmarks partitioned on a single-chip microprocessor/FPGA device.

关键词： hardware/software partitioning synthesis binary translation decompilation low power assembly language FPGA codesign synthesis

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