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Theoretical and practical aspects of computer speech processing

Theoretical and practical aspects of computer speech process...

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IEEE international conference on Cognitive Informatics

作者： Z. Ciota Department of Microelecronic and Computer Science Technical University of Lodz Poland

The design process of computer speech systems is presented. Going over the solutions of neural networks, the systolic structure gives the biggest possibility for smart realization of a speech processor. A speech processing system, built generally as software surroundings, occupies an immense memory space. For real-time application it is necessary to combine the existing algorithms. Further increasing of the speed can be also achieved by using hardware-software co-design. The approach presented in this paper, permits to design such effective systems of human voice synthesis and speech identification. Since the spoken language can be very often ambiguous, then it was useful to include a fuzzy logic approach and also artificial neural networks, to obtain more effective methods of speech processing. Mixed analog-digital realizations are also discussed. Practical realizations of the current mode building blocks ensure the cheapest realization of CMOS integrated circuits.

关键词： Speech processing Speech synthesis Process design Neural networks Application software Human voice Network synthesis Natural languages Fuzzy logic Artificial neural networks

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Optimization of a retargetable functional simulator for embedded processors

Optimization of a retargetable functional simulator for embe...

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international conference and Workshop on Engineering of Computer-Based systems

作者： F. Papariello G. Luculli Advanced System Technology STMicroelectronics Grenoble France

ISBN: (纸本)0769515495

The objective of this research is to develop tools and methods for system-level optimization of embedded software that is executed on system-on-chip platforms. In particular, this paper proposes a new instruction-set simulator's tool flow which has been extended with some retargetability features and multiple program representations. We propose an innovative way to improve the simulation speed, that is a key factor for embedded software optimization, by using a synthesis approach. In depth description is reported of the source-level optimization of the simulation library which is an important part of such new mechanism. Experimental results show a speedup of about 24 for the throughput of the simulation library, reaching the valuable performance of 50 Mops.

关键词： hardware Embedded software Instruction sets system-on-a-chip software libraries Computational modeling software design Design optimization Process design Optimization methods

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hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs

Hardware-software co-synthesis of low power real-time distri...

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Asia and South Pacific Design Automation conference

作者： L. Shang N.K. Jha Department of EE Princeton University USA

ISBN: (纸本)0769514413

In this paper, we present a multi-objective hardware-software co-synthesis system for multi-rate, real-time, low power distributed embedded systems consisting of dynamically reconfigurable FPGAs, processors, and other system resources. We use an evolutionary algorithm based framework for automatically determining the quantity and type of different system resources, and then assigning tasks to different processing elements (PEs) and task communications to communication links. For FPGAs, we propose a two-dimensional, multi-rate cyclic scheduling algorithm, which determines task priorities based on real-time constraints and reconfiguration overhead information, and then schedules tasks based on the resource utilization and reconfiguration condition in both space and time. The FPGA scheduler is integrated in a list-based system scheduler. To the best of our knowledge, this is the first multi-objective co-synthesis system, which uses dynamically reconfigurable devices to synthesize a distributed embedded system, to target simultaneous optimization of system price and power. Experimental results indicate that our method can reduce schedule length by an average of 41.0% and reconfiguration power by an average of 46.0% compared to the previous method. It also yields multiple system architectures which trade off system price and power under real-time constraints.

关键词： Real time systems Embedded system Field programmable gate arrays Energy consumption Evolutionary computation Resource management Scheduling algorithm hardware Reconfigurable architectures Contracts

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High-level synthesis with SIMD units

High-level synthesis with SIMD units

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Asia and South Pacific Design Automation conference

作者： V. Raghunathan A. Raghunathan M.B. Srivastava M.D. Ercegovac Department of Electrical Engineering University of California Los Angeles CA USA C & C Research Laboratories NEC USA Inc. Princeton NJ USA Department of Computer Science University of California Los Angeles CA USA

ISBN: (纸本)0769514413

This paper presents novel techniques to integrate the use of Single Instruction Multiple Data (SIMD) functional units in a high-level synthesis (HLS) design methodology. SIMD functional units can be configured to operate in one or more SIMD modes, in which they process multiple sets of smaller bitwidth operands in parallel. Conceptually, the use of SIMD functional units enables HLS to (i) exploit parallelism to a higher degree without using additional resources, (ii) improve resource utilization by enabling hardware re-use at a fine-grained level, and (iii) improve energy efficiency for a given area and/or performance constraint. We illustrate the issues involved in performing high-level synthesis with SIMD functional units, and discuss how algorithms involved in a typical high-level synthesis flow can be enhanced to result in maximal performance and energy improvements. These techniques are not restricted to specific high-level synthesis tools/algorithms, and can be plugged into any generic high-level synthesis system.

关键词： High level synthesis Computer architecture hardware Space exploration Application software Arithmetic Logic Circuits Computer science High performance computing

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A strongly polynomial-time algorithm for over-constraint resolution: efficient debugging of timing constraint violations 02

A strongly polynomial-time algorithm for over-constraint res...

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proceedings of the tenth international symposium on hardware/software codesign

作者： Ali Dasdan Synopsys Inc. Mountain View CA

ISBN: (纸本)9781581135428

A system of binary linear constraints or difference constraints (SDC) contains a set of variables that are constrained by a set of unary or binary linear inequalities. In such diverse applications as scheduling, interface timing verification, real-time systems, multimedia systems, layout compaction, and constraint satisfaction, SDCs have successfully been used to model systems of both temporal and spatial constraints. Formally, SDCs are modeled by weighted, directed (constraint) graphs. The consistency of an SDC means that there is at least one instantiation of its variables that satisfies all its constraints. It is well known that the absence of positive cycles in a graph implies the consistency of the corresponding SDC, so the consistency can be decided in strongly polynomial time. If a SDC is found to be inconsistent, it has to be repaired to make it consistent. This task is equivalent to removing positive cycles from the corresponding graph. All the previous algorithms for this task take time proportional to the number of positive cycles in the graph, which can grow exponentially. In this paper, we propose a strongly polynomial-time algorithm, i.e., an algorithm whose time complexity is polynomial in the size of the graph. Our algorithm takes in a graph and returns a list of edges and the changes in their weights to remove all the positive cycles from the graph. We experimentally quantify the length of the edge list and the running time of the algorithm on large benchmark graphs. We show that both are very small, so our algorithm is practical.

关键词： timing constraints rate analysis high-level synthesis constraint satisfaction behavioral synthesis scheduling

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Architecture implementation using the machine description language LISA

Architecture implementation using the machine description la...

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Asia and South Pacific Design Automation conference

作者： O. Schliebusch A. Hoffmann A. Nohl G. Braun H. Meyr RWTH Integrated Signal Processing Systems Aachen Germany

ISBN: (纸本)0769514413

The development of application specific instruction set processors comprises several design phases: architecture exploration, software tools design, system verification and design implementation. The LISA processor design platform (LPDP) based on machine descriptions in the LISA language provides one common environment for these design phases. Required software tools for architecture exploration and application development can be generated from one sole specification. This paper focuses on the implementation phase and the generation of synthesizable HDL code from a LISA model. The derivation of the architectural structure, decoder and even approaches for the implementation of the data path are presented. Moreover the synthesis results of a generated and a handwritten implementation of a low-power DVB-T post processing unit are compared.

关键词： Computer architecture software tools software design hardware design languages Application software Signal design Process design Application specific processors Registers Signal processing

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proceedings of the ninth international symposium on hardware/software codesign

Proceedings of the ninth international symposium on hardware...

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9th international Symposium on hardware/software codesign

The proceedings contains 43 papers from the conference on the proceedings of the Ninth international Symposium on hardware/software codesign. Topic discussed include: the usage of stochastic processes in embedded system specifications;modelling and evaluation of hardware/software designs;a practical toolbox for system level communication synthesis;designing domain-specific processors;a novel parallel deadlock detection algorithm and architecture;towards effective embedded processors in codesigns: customizable partitioned caches;and development cost and size estimation starting from high-level specifications.

关键词： Embedded systems

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A practical tool box for system level communication synthesis 01

A practical tool box for system level communication synthesi...

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9th international Symposium on hardware/software codesign (CODES 2001)

作者： Hommais, D Pétrot, F Augé, I Univ Paris 06 Equipe ASIM LIP6 Paris France

ISBN: (纸本)1581133642

This paper presents a practical approach to communication synthesis for hardware/software system specified as tasks communicating through lossless blocking channels. It relies on a limited set of templates that characterize the way data an exchanged between tasks realized either in software or in hardware. The templates are highly portable because their software part is implemented using the POSIX thread functions, and their hardware part is a hand crafted synthesizable module with a system VCI interface. These Interface Modules allow simple Virtual Component reuse since they not only implement protocol compatibility through the use of the system VCI/OCB standard but also system level communications through semantics widely accepted in the design community.

关键词： hardware Permission Yarn Computer architecture Protocols Virtual manufacturing Writing Resumes

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Generating mixed hardware/software systems from SDL specifications

Generating mixed hardware/software systems from SDL specific...

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9th international Symposium on hardware/software codesign (CODES 2001)

作者： Slomka, F Dörfel, M Münzenberger, R Univ Erlangen Nurnberg Dept Comp Networks & Commun Syst D-91058 Erlangen Germany

ISBN: (纸本)1581133642

A new approach for the translation of SDL specifications To a mixed hardware/software system is presented. Based on the computational model of communicating extended finite state machines (EFSM) the control flow is separated from dataflow of the SDL process. Hence for the first time it is possible to generate a mired hardware/software implementation of an SDL process. This technique also reduces the complexity for high-level and register-transfer synthesis tools for the hardware parts of the system. The advantage of this methodology ir shown by a design example of a wireless communication chip.

关键词： High level languages

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Formal synthesis and code generation of embedded real-time software 01

Formal synthesis and code generation of embedded real-time s...

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9th international Symposium on hardware/software codesign (CODES 2001)

作者： Hsiung, PA Natl Chung Cheng Univ Inst Comp Sci & Informat Engn Chiayi 621 Taiwan

ISBN: (纸本)1581133642

Due to rapidly increasing system complexity, shortening time-to-market, and growing demand for hard real-time system, formal methods am becoming indispensable in the synthesis of embedded system, which must satisfy stringent temporal, memory. and environment constraints. There is a general lack of practical formal methods that can synthesize complex embedded real-time software (ERTS). In this work, a formal method based on Time Free-Choice Petri Nets (TFCPN) is proposed for ERTS synthesis. The synthesis method employs quasi-static data scheduling for satisfying limited embedded memory requirements and uses dynamic realtime scheduling for satisfying hard real-time constraints. software code is then generated from a set of quasi-statically and dynamically scheduled TFCPNs. Finally, an application example is given to illustrate the feasibility of the proposed TFCPN-bssed formal method for ERTS synthesis.

关键词： embedded real-time software Petri Nets scheduling code generation

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