In this work, a generic Integer Programming (IP) model for hardware/softwarecodesign is presented Efficient behavioral description of the required problem space is first developed using a high level procedural langua...
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ISBN:
(纸本)0780374061
In this work, a generic Integer Programming (IP) model for hardware/softwarecodesign is presented Efficient behavioral description of the required problem space is first developed using a high level procedural language. This behavioral model serves two purposes;system-level simulations, partitioning analysis. This behavioral model is used to generate a cost matrix for till system level modules. First, the behavioral model is used to determine the cost of program and data memory. Secondly, the behavioral code is profiled to generate information about module execution overhead. Inter-module communication cost is determined using the module call-flow graph. A cost matrix is developed for the modules. Each column of the cost matrix is given appropriate weight and an IP model is solved to make a decision whether a module is to be implemented in hardware or software.
We review the use of nondeterminism and identify two different purposes. The descriptive purpose handles uncertainties in the behaviour of existing entities. The constraining purpose is used in specifications to const...
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ISBN:
(纸本)1581133642
We review the use of nondeterminism and identify two different purposes. The descriptive purpose handles uncertainties in the behaviour of existing entities. The constraining purpose is used in specifications to constrain implementations. For the specification of embedded systems we suggest a stochastic process sigma instead of nondeterminism. It serves mostly the descriptive purpose but can also be used to constrain the system. We carefully distinguish different interpretations of these concepts by the different design activities simulation, synthesis and verification.
We introduce a formal basis for viewing computer systems as mixed steady state and non-steady state (transient) behaviors to motivate novel design strategies resulting from simultaneous consideration of function, sche...
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ISBN:
(纸本)1581134185
We introduce a formal basis for viewing computer systems as mixed steady state and non-steady state (transient) behaviors to motivate novel design strategies resulting from simultaneous consideration of function, scheduling and architecture. We relate three design styles: hierarchical decomposition, static mapping and directed platform that have traditionally been separate. By considering them together, we reason that once a steady state system is mapped to an architecture, the unused processing and communication power may be viewed as a platform for a transient system, ultimately resulting in more effective design approaches that ease the static mapping problem while still allowing for effective utilization of resources. Our simulation environment frequency interleaving, mixes a formal and experimental approach as illustrated in an example.
The paper puts forward a sort of realizing project of direct torque control (DTC) system of permanent magnet synchronous motor based on DSP. It mainly introduces the theory of the system's realization and the desi...
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ISBN:
(纸本)7506251159
The paper puts forward a sort of realizing project of direct torque control (DTC) system of permanent magnet synchronous motor based on DSP. It mainly introduces the theory of the system's realization and the design method of software and hardware. Through experiments it indicates the feasibility of the projects and displays the prominence of the chip.
In this paper, we outline a new approach to safety analysis in which concepts of computer HAZOP are fused with the idea of software fault tree analysis to enable a continuous assessment of an evolving programmable des...
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ISBN:
(纸本)0769511023
In this paper, we outline a new approach to safety analysis in which concepts of computer HAZOP are fused with the idea of software fault tree analysis to enable a continuous assessment of an evolving programmable design developed in Matlab-Simulink. We also discuss the architecture of a tool that we have developed to support the new method and enable its application in complex environments. We show that the method and the tool enable the integrated hardware and software analysis of a programmable system and that in the course of that analysis they automate and simplify the development of fault trees for the system. Finally, we propose a demonstration of the method and the tool and ive outline the experimental platform and aims of that demonstration.
The Princeton Sound Kitchen is a repository of open source software for computer music written by graduate students and professors of the computer science and music departments at Princeton University. This studio rep...
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This paper describes a senior capstone design project in computer engineering that incorporates the concept of hardware/ softwarecodesign. Details of the project, required infrastructure and tools, and results of the...
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ISBN:
(纸本)0769511562
This paper describes a senior capstone design project in computer engineering that incorporates the concept of hardware/ softwarecodesign. Details of the project, required infrastructure and tools, and results of the first implementation of this project are described.
Describes a new approach to hardware/softwarecodesign for complex embedded systems, using high-level programming languages, such as C, C++, Java, or Ada. Unlike previous approaches, we do not distribute parts of the ...
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Describes a new approach to hardware/softwarecodesign for complex embedded systems, using high-level programming languages, such as C, C++, Java, or Ada. Unlike previous approaches, we do not distribute parts of the behavior between the different subsystems. We map the entire behavior onto the whole system, and the partition is made implicitly during the synthesis process. We divide the system specification into behavior, architecture and design criteria, to maximize reuse opportunities and to increase the flexibility of the design environment.
The proceedings contain 31 papers. The topics discussed include: design space characterization for architecture/compiler co-exploration;storage allocation for embedded processors;an empirical evaluation of high level ...
ISBN:
(纸本)1581133995
The proceedings contain 31 papers. The topics discussed include: design space characterization for architecture/compiler co-exploration;storage allocation for embedded processors;an empirical evaluation of high level transformations for embedded processors;a novel approach to code analysis of digital signal processing systems;the very portable optimizer for digital signal processors;patchable instruction ROM architecture;hardware compilation of sequential Ada;a new method for compiling schizophrenic synchronous programs;transparent data-memory organizations for digital signal processors;a vision for embedded software;combined partitioning and data padding for scheduling multiple loop nests;heterogeneous memory management for embedded systems;establishing a tight bound on task interference in embedded system instruction caches;personal, handheld, wireless: the future of digital technology;pattern matching in reconfigurable logic for packet classification;personal, handheld, wireless: the future of digital technology;efficient longest executable path search for programs with complex flows and pipeline effects;and tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures.
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory system-on-a-Chip implementation. These overheads are observed in terms of lock latency, lock delay and memory bandw...
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ISBN:
(纸本)1581133995
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory system-on-a-Chip implementation. These overheads are observed in terms of lock latency, lock delay and memory bandwidth consumption in the system. It has been shown that a hardware solution brings a much better performance improvement than the synchronization algorithms developed in software [3]. Our previous work presented a SoC Lock Cache (SoCLC) hardware mechanism which resolves the Critical Section (CS) interactions among multiple processors and improves the performance criteria in terms of lock latency, lock delay and bandwidth consumption in a shared memory multiprocessor SoC for short CSes [1]. This paper extends our previous work to support long CSes as well. This combined support involves modifications both in the RTOS kernel filevel facilities (such as support for preemptive versus non-preemptive synchronization, interrupt handling and RTOS initialization) and in the hardware mechanism. The worst-case simulation results of a database application model with client-server pair of tasks on a fourprocessor system showed that our mechanism achieved a 57% improvement in lock latency, 14% speed up in lock delay and a 35% overall speedup in total execution time. Copyright 2001 ACM.
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