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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1553 条记录，以下是1201-1210 订阅

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Generating mixing hardware/software systems from SDL specifications 01

Generating mixing hardware/software systems from SDL specifi...

引用

proceedings of the ninth international symposium on hardware/software codesign

作者： Frank Slomka Matthias Dörfel Ralf Münzenberger University of Erlangen-Nuremberg Department of Computer Networks and Communication Systems Martensstr. 3 91058 Edangen Germany

ISBN: (纸本)9781581133646

A new approach for the translation of SDL specifications to a mixed hardware/software system is presented. Based on the computational model of communicating extended finite state machines (EFSM) the control flow is separated from data flow of the SDL process. Hence for the first time it is possible to generate a mixed hardware/software implementation of an SDL process. This technique also reduces the complexity for high-level and register-transfer synthesis tools for the hardware parts of the system. The advantage of this methodology is shown by a design example of a wireless communication chip.

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CODEF: A system level design space exploration tool

CODEF: A system level design space exploration tool

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IEEE international conference on Acoustics, Speech, and Signal Processing

作者： Auguin, M Capella, L Cuesta, F Gresset, E Univ Nice Sophia Antipolis Lab I3S Nice France

ISBN: (纸本)0780370414

The increasing complexity of embedded applications combined with the advances in chip integration make the design process a very challenging task. Due to this rising complexity, the design under performance, area and consumption constraints of a system-on-a-chip (SOC) composed of mixed software-hardware units, becomes increasingly intricate. This paper presents a method and an associated tool (CODEF) which allow the designer to do an automatic and/or interactive system design space exploration in order to construct cost effective embedded real-time architectures dedicated to complex signal processing applications. The method is based on a recursive partitioning algorithm followed by a communication synthesis procedure.

关键词： Embedded systems

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11th international conference on Field-Programmable Logic andApplications 2001

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11th international conference on Field-Programmable Logic and Applications, FPL 2001

ISBN: (纸本)3540424997

The proceedings contain 74 papers. The special focus in this conference is on Invited Keynote 1 and Architectural Frameworks. The topics include: Technology trends and adaptive computing;prototyping framework for reconfigurable processors;an emulator for exploring RaPiD configurable computing architectures;a new placement method for direct mapping into LUT-based FPGAs;fGREP - fast generic routing demand estimation for placed FPGA circuits;macrocell architectures for product term embedded memory arrays;gigahertz reconfigurable computing using SiGe HBT BiCMOS FPGAs;memory synthesis for FPGA-based reconfigurable computers;implementing a hidden markov model speech recognition system in programmable logic;implementation of (normalised ) RLS lattice on virtex;accelerating matrix product on reconfigurable hardware for signal processing;static profile-driven compilation for FPGAs;synthesizing RTL hardware from java byte codes;from behavioral specification to multi-FPGA-prototype;secure configuration of field programmable gate arrays;single-chip FPGA implementation of the advanced encryption standard algorithm;jbits™ implementations of the advanced encryption standard (rijndael );task-parallel programming of reconfigurable systems;chip-based reconfigurable task management;configuration caching and swapping;multiple stereo matching using an extended architecture;implementation of a NURBS to bézier conversor with constant latency;reconfigurable frame-grabber for real-time automated visual inspection (RT-AVI ) systems;processing models for the next generation network;tightly integrated placement and routing for FPGAs;a tool for the simultaneous placement and detailed routing of gate-arrays;reconfigurable router modules using network protocol wrappers;development of a design framework for platform-independent networked reconfiguration of software and hardware and the molen ρμ-coded processor.

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A theory of combinational programs

A theory of combinational programs

引用

Asia-Pacific conference on software Engineering

作者： T. Van Dung H. Jifeng International Institute for Software Technology United Nations University Macao China

ISBN: (纸本)0769514081

The actual behaviour of a hardware device available for an implementation of a control system can be simulated by a program, allowing the hardware device to be proved correct by standard software techniques. In this paper we formalise event semantics of hardware description language in the form of relations and use relation calculus to prove properties (including termination, stability, and uniqueness of final state) of combinational programs, the cycle behaviour of which is defined as a conditional loop of non-deterministic choices between generalised parallel assignments.

关键词： hardware design languages Computational modeling Helium Control system synthesis software standards Calculus Stability Discrete event simulation Wires Registers

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IFIP WG10.3/WG10.4/WG10.5 international Workshop on Distributed and Parallel Embedded systems, DIPES 2000

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IFIP WG10.3/WG10.4/WG10.5 international Workshop on Distributed and Parallel Embedded systems, DIPES 2000

ISBN: (纸本)9781475745351

The proceedings contain 22 papers. The special focus in this conference is on Distributed and Parallel Embedded systems. The topics include: A Methodology for Complex Embedded systems Design;Analog/Digital Co-Design;A Design Methodology for Embedded systems based on Multiple Processors;An Architecture for Reliable Distributed Computer-Controlled systems;Generic Architecture Platform for Multiprocessor system-On-Chip Design;Optimizing Functional distribution in Complex system Design;Customizing software Toolkits for Embedded systems-On-Chip;Framework for system Design, Validation and Fast Prototyping of Multiprocessor system-On-Chip;Real-Time Support for Online Controller Supervision and Optimisation;A Product Family Approach to Graceful Degradation;Environment Modelling in Closed Specifications of Embedded systems;Test Case Design for the Validation of Component-Based Embedded systems;Timing Constraints Validation using UPPAAL;A New Dynamic Scheduling Algorithm for Real-Time Multiprocessor systems;Deriving Message Passing Protocols from Collective Behavior;Java Real-Time Publish-Subscribe Middleware for Distributed Embedded systems;A Verified hardware synthesis of Esterel Programs and Automatic Code Generation for Multirate Simulink Models with Support for the OSEK Real-Time Operating system.

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A structured approach to embedded control systems implementation

A structured approach to embedded control systems implementa...

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IEEE conference on Control Technology and Applications (CCTA)

作者： J.F. Broenink G.H. Hilderink Control Laboratory Faculty EE University of Twente Enschede Netherlands

The method presented aims at supporting the development of control software for embedded control systems. The method considers the implementation process as a stepwise refinement from physical system models and control laws to efficient control computer code, and that all phases are verified by simulation. Simulation is also used as a verification tool during physical system modeling and control law development. Data flow diagrams are used to describe the control software throughout the whole implementation process. Since we aim at heterogeneous distributed processors as target hardware, we use a link driver library based on the CSP channel concept. Communication peculiarities are encapsulated by the link drivers.

关键词： Control systems Embedded software Home appliances Control system synthesis Computational modeling Communication system control Embedded system Vehicle dynamics hardware software systems

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Speed and resource issues on algorithm design and implementation with hardware

Speed and resource issues on algorithm design and implementa...

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international conference on ASIC

作者： Dai Zibin Zhang Shunxin The PLA Information Engineering University Zhengzhou China

Speed and resource issues on algorithm design and implementation with hardware are discussed in this paper. Two approaches to improve system-processing speed and to save logic resource have been proposed. Furthermore,... 详细信息

关键词： Algorithm design and analysis hardware Logic devices Logic functions Computer aided software engineering Circuit synthesis Logic design Logic circuits Delay Clocks

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An efficient timing model for hardware implementation of multirate dataflow graphs

An efficient timing model for hardware implementation of mul...

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international conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Nitin Chandrachoodan Shuvra S Bhattacharyaa K.J. Ray Liu Department of Electrical and Computer Engineering University of Maryland College Park MD USA University System of Maryland Adelphi MD US

We consider the problem of representing timing information associated with functions in a dataflow graph used to represent a signal processing system in the context of high-level hardware (architectural) synthesis. This information is used for synthesis of appropriate architectures for implementing the graph. Conventional models for timing suffer from shortcomings that make it difficult to represent timing information in a hierarchical manner, especially for multirate signal processing systems. We identify some of these shortcomings, and provide an alternate model that does not have these problems. We show that with some reasonable assumptions on the way hardware implementations of multirate systems operate, we can derive general hierarchical descriptions of multirate systems similarly to single rate systems. Several analytical results such as the computation of the iteration period bound, that previously applied only to single rate systems can also easily be extended to multirate systems under the new assumptions. We have applied our model to several multirate signal processing applications, and obtained favorable results. We present results of the timing information computed for several multirate DSP applications that show how the new treatment can streamline the problem of performance analysis and synthesis of such systems.

关键词： Timing hardware Digital signal processing Delay Signal synthesis High level synthesis Computer architecture Context modeling Signal processing Application software

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CODEF: a system level design space exploration tool

CODEF: a system level design space exploration tool

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international conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： M. Auguin L. Capella F. Cuesta E. Gresset Laboratoire I3S Université de Nice Sophia Antipolis France Philips Semiconductors La Valbonne France

关键词： system-level design Space exploration Application software system-on-a-chip Signal design Signal processing algorithms Process design Interactive systems Costs Real time systems

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The IBM Personal Speech Assistant

The IBM Personal Speech Assistant

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international conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： L. Comerford D. Frank P. Gopalakrishnan R. Gopinath J. Sedivy IBM Thomas J. Watson Research Center Yorktown Heights NY USA

We describe technology and experience with an experimental personal information manager, which interacts with the user primarily but not exclusively through speech recognition and synthesis. This device, which controls a client PDA, is known as the personal speech assistant (PSA). The PSA contains complete speech recognition, speech synthesis and dialog management systems. Packaged in a hand-sized enclosure, of size and physical design to mate with the popular Palm III personal digital assistant, the PSA includes its own battery, microphone, speaker, audio input and output amplifiers, processor and memory. The PSA supports speaker-independent English speech recognition using a 500-word vocabulary, and English speech synthesis on an arbitrary vocabulary. We survey the technical issues we encountered in building the hardware and software for this device, and the solutions we implemented, including audio system design, power and space budget, speech recognition in adverse acoustic environments with constrained processing resources, dialog management, appealing applications, and overall system architecture.

关键词： Speech recognition Speech synthesis Personal digital assistants Vocabulary Information management Technology management Control system synthesis Packaging Batteries Microphones

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