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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

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How to improve the space utilization of dedup-based PCM storage devices? 15

How to improve the space utilization of dedup-based PCM stor...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Chun-Ta Lin Yuan-Hao Chang Tei-Wei Kuo Hung-Sheng Chang Hsiang-Pang Li Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan R.O.C. Institute of Information Science Academia Sinica Taipei Taiwan R.O.C. Research Center for Information Technology Innovation Academia Sinica Taipei Taiwan R.O.C. Macronix International Co. Ltd. Emerging System Lab. Hsinchu Taiwan R.O.C.

ISBN: (纸本)9781467383219

There is a growing demand to introduce more and more intelligence to storage devices in recent years, especially with the rapid increasing of hardware computing power. This paper targets on essential design issues in space utilization for dedup-based non-volatile phase-change memory (PCM). We explore the adoption of data duplication techniques to reduce potential data duplicates over PCM storage devices to provide more storage space than the physical storage space does. Among various data deduplication techniques, variable-sized chunking is considered in less cost-effective PCM-based storage devices because variable-sized chunking has better data deduplication capability than fixed-sized chunking. However, in a typical system architecture, data are written or updated in the fixed management units (e.g., LBAs). Thus, to ultimately improve the space utilization of PCM-based storage device, the technical problem falls on (1) how to map fixed-sized LBAs to variable-sized chunks and (2) how to efficiently manage (i.e., allocated and deallocate) free PCM storage space for variable-sized chunks. In this work, we propose a free space manager, called container-based space manager, to resolve the above two issues by exploiting the fact that (1) a storage system initially has more free space to relax the complexity on space management and (2) the space optimization of a storage system can grow with the time when it contains more and more data. The proposed design is evaluated over popular benchmarks, for which we have very encouraging results.

关键词： Phase change materials Power capacitors Performance evaluation Ash Computer architecture Random access memory Media

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A hardware-efficient frequency domain correlator architecture for acquisition stage in GPS

A hardware-efficient frequency domain correlator architectur...

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international conference on Reconfigurable Computing and FPGAs

作者： Romero-Aguirre, E. Parra-Michel, R. Longoria-Gandara, O. Aguirre-Hernández, M. Dept. of Electrical Engineering CINVESTAV-IPN Mexico Electronics Systems and Computer Sc. Department ITESO Mexico Comms. Research Center Mexico Intel Corp. Jalisco Mexico

ISBN: (纸本)9780769543147

A frequency domain correlator (FDC) with low-complexity architecture is proposed. This signal processing module is part of FFT-based acquisition stage of a global position system (GPS). The FDC is based on a single reconfigurable core capable of computing both decimation in frequency radix-2 (DIF-2) fast Fourier transform (FFT) and decimation in time radix-2 (DIT-2) inverse fast Fourier transform (IFFT). The proposed FDC reuses the reconfigurable core together with appropriate decimation choice, providing an improvement in resource management while avoiding any additional reorder data hardware. Additionally, the FDC architecture shows a great flexibility due to three levels of parameterization which allows to fix the number of complex input samples, data width and word format. The architecture has been implemented in Altera Cyclone II and Xilinx Virtex II Pro for N-points correlation with different word lengths. The simulation and synthesis results shows that the FDC is suitable for performing acquisition stage in GPS, enabling its utilization in software define radios. © 2010 IEEE.

关键词： Global positioning system

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hardware/software partitioning using integer programming 96

Hardware/software partitioning using integer programming

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European Design and Test (ED&TC) conference

作者： R. Niemann P. Marwedel Department of Computer Science XII University of Dortmund Dortmund Germany

ISBN: (纸本)9780818674235

One of the key problems in hardware/software codesign is hardware/software partitioning. This paper describes a new approach to hardware/software partitioning using integer programming (IP). The advantage of using IP is that optimal results are calculated respective to the chosen objective function. The partitioning approach works fully automatic and supports multi-processor systems, interfacing and hardware sharing. In contrast to other approaches where special estimators are used, we use compilation and synthesis tools for cost estimation. The increased time for calculating the cost metrics is compensated by an improved quality of the estimations compared to the results of estimators. Therefore, fewer iteration steps of partitioning will be needed. The paper shows that using integer programming to solve the hardware/software partitioning problem is feasible and leads to promising results.

关键词： hardware Linear programming Iterative algorithms Partitioning algorithms Cost function Embedded system Processor scheduling software algorithms Application software Digital signal processing

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Guided anti-tank missile control training simulator design via object-oriented modelling

Guided anti-tank missile control training simulator design v...

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proceedings of the 1998 international conference on Control. Part 2 (of 2)

作者： Mohenski, Darko D. Dimirovski, Georgi M. Deskovski, Stojce M. Military Acad of RM 'General M. Apostolski' Skopje Macedonia

A PC platform based training simulator for personnel on anti-tank guided missile (ATGM) systems has been designed and implemented as a complex system which is controlled by instructor-trainee interaction. It makes use of object oriented simulation modelling, 6DOF missile model and mask modelling of terrain and weather conditions. To cope with the system complexity, both a modular designs of the system and its subsystems is adopted, and an object-oriented programming is applied. A fully elaborated set of compatible models and respective software implementations for missile and moving ground target involving their interrelated kinematics has been developed. An appropriate user-system interface has been designed to enhance instructor-trainee co-operation. It is aimed both for simulation studies of anti-tank combat (ATC) using command-to-line-of-sight (CLOS) guided missiles and for training operators of such systems. An implemented hardware-in-the-loop (HIL) element in the system is the real guidance system. Sample results for an experimental session with real-world data and situation are given.

关键词： Control system synthesis

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High-level Synthesizable Dataflow MapReduce Accelerator for FPGA-coupled Data Centers 15

High-level Synthesizable Dataflow MapReduce Accelerator for ...

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international conference on Embedded Computer systems Architectures Modeling and Simulation

作者： Diamantopoulos, Dionysios Kachris, Christoforos Natl Tech Univ Athens Sch Elect & Comp Engn GR-10682 Athens Greece Democritus Univ Thrace Dept Elect & Comp Engn Xanthi Greece

ISBN: (纸本)9781467373111

Manipulating big-data entries of emerging server workloads requires a design paradigm shift towards more aggressive system-level architecture solutions. From software perspective, the MapReduce framework is a prominent parallel data processing tool as the volume of data to analyze grows rapidly. FPGAs can be used to accelerate the processing of data and reduce significantly the power consumption. However, FPGAs have not been deployed in data centers due to the high programming complexity of hardware. In this paper we present HLSMapReduceFlow, i.e. a novel reconfigurable MapReduce accelerator that can be scaled-up to data centers and it can speedup the processing of Map computation kernels, while promising minimum energy footprint and high programming efficiency due to the use of HLS. We propose the complete decoupling of MapReduce's tasks data-paths to distinct buses, accessed from individual processing engines. Such a dataflow approach implies a holistic C/C++ to RTL domain-level MapReduce transition. In this work, we further extent HLS tools, with systematic source to-source code annotation of HLS optimization directives, by adding as a state-of-art system-level implementation toolfiow. The proposed architecture is implemented, mapped and evaluated to a Virtex-7 FPGA and shows that the proposed scheme can achieve up to 43 x overall throughput improvement in MapReduce applications, while offering two orders of magnitude power/energy improvements compared to a high-end multi-core processor.

关键词： MapReduce hardware accelerator High-Level synthesis Reconfigurable computing Dataflow computing

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A hardware filesystem implementation for high-speed secondary storage

A hardware filesystem implementation for high-speed secondar...

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2008 international conference on Reconfigurable Computing and FPGAs, ReConFig 2008

作者： Mendon, Ashwin A. Sass, Ron Electrical and Computer Engineering Department University of North Carolina Charlotte 9201 University Blvd. Charlotte NC 28223 United States

ISBN: (纸本)9780769534749

Platform FPGAs are capable of hosting entire Linux-based systems including standard peripherals, integrated network interface cards and even disk controllers on a single chip. Filesystems, however, are typically implemented in software as part of the operating system. This presents a challenge as some applications are very sensitive to file I/O latency and Platform FPGA processor cores are clocked at relatively slow frequencies. This paper describes a design and implementation of a filesystem in hardware. A hardware implementation offers several features that have potential of improving certain classes of applications. The filesystem implemented is a simplified version of the well-known UNIX filesy stem and specifically designed to handle a relatively low number of very large files. The design synthesizes but lacks a SATA host controller needed to test it. Instead, Modelsim was used to verify the functionality of four basic operations: open, read, write and remove. synthesis results show that the core uses a modest 3% of the slices (and 3 BRAM blocks) of a Xilinx Virtex-4 FX60 device. By using a behavioral model of a SATA disk controller, sequential read bandwidth simulations achieved over 3 Gb/s for block sizes of 512 bytes. Since physical disks are much slower, these results suggest that a hardware filesystem core offers several benefits with little cost and no loss of performance. © 2008 IEEE.

关键词： Field programmable gate arrays (FPGA)

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On lifting of statechart structuring mechanisms

On lifting of statechart structuring mechanisms

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international conference on Application of Concurrency to system Design

作者： L. Gomes A. Costa Centro de Robótica Inteligente UNINOVA Portugal Faculdade de Ciências e Tecnologia Department of Electrical Engineering Universidade Nova de Lisboa Portugal

We propose a set of procedures addressing the implementation of statechart models. The main goal of this set of procedures is to lift the structuring mechanisms presented in statecharts to the top level. In this sense, the complexity of statechart implementation will be similar to the complexity of communicating concurrent state machines and the platforms selected to support implementation will not need to have specific capabilities to directly support the structuring mechanisms of Harel's statecharts. The framework is the design of embedded systems (in the sense of reactive realtime systems) and automation applications, either industrial automation or building automation, either the emphasis is on system, hardware or software levels, using or not codesign techniques. An application focused on hardware implementation using VHDL as implementation language is used as an example.

关键词： Object oriented modeling History Design automation Application software hardware Concurrent computing Embedded system Computer industry Buildings Embedded software

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Special Session: Neuro-Symbolic Architecture Meets Large Language Models: A Memory-Centric Perspective

Special Session: Neuro-Symbolic Architecture Meets Large Lan...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Mohamed Ibrahim Zishen Wan Haitong Li Priyadarshini Panda Tushar Krishna Pentti Kanerva Yiran Chen Arijit Raychowdhury Georgia Institute of Technology Purdue University Yale University University of California Berkeley Duke University

ISBN: (数字)9798350356397

ISBN: (纸本)9798350356403

Large language models (LLMs) have significantly transformed the landscape of artificial intelligence, demonstrating exceptional capabilities in natural language understanding and generation. Recently, the integration of LLMs with neurosymbolic architectures has gained traction to enhance contextual awareness and planning capabilities. However, this integration faces computational challenges that hinder scalability and efficiency, especially in edge computing environments. This paper provides an in-depth analysis of these challenges and explores state-of-the-art solutions, focusing on memory-centric computing principles at both algorithmic and hardware levels. Our exploration is centered around the key computational elements of the Transformer, the foundation of all LLMs, and vector-symbolic architecture, the leading neuro-symbolic model for edge applications. Additionally, we propose potential research directions for further investigation. By examining these aspects, this paper aims to bridge critical gaps in the path toward effective artificial general intelligence at the edge.

关键词： Computational modeling Scalability Large language models Focusing Computer architecture Transformers hardware Natural language processing Planning Optimization

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Simulation of Model Based system Design Using Real Time Windows

Simulation of Model Based System Design Using Real Time Wind...

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12th World Multi-conference on systemics, Cybernetics and Informatics/14th international conference on Information systems Analysis and synthesis

作者： Moin, Lubna Ali, Shahid Uddin, Vali Natl Univ Sci & Technol Pakistan Engn Coll Karachi Pakistan

ISBN: (纸本)9781934272336

Real-time systems are loosely defined as the class of computer systems that interact with the external world in a time frame defined by the external world. It is an environment where a single computer is a host and a target. After creating a model and simulating it with simulink in normal mode we can generate executable codes with real time workshop. Here we have used MATLAB as an application tool which provide us the specialized tool boxes for specific areas. The real time window target communicates with the executable program acting as a control program and interfaces with the hardware device through the I/O port. Here we tried to analyse a magnetic levitation system. The control goal is to suspend a steel sphere by means of a magnetic field counteracting the force of gravity and to be able to apply a controlled disturbance to force the sphere to follow a predetermined trajectory. The control to be applied is the voltage, which is converted into a current via internal circuitry in the controller located in the mechanical unit. The current passes through and an electromagnet which creates a magnetic field in its vicinity. The sphere is placed along the vertical axis of the electromagnet after the control system is started in the software. In this way a approach towards real time workshop is analysed and applied.

关键词： Magnetic levitation PID controller actuator sensor real time MATLAB simulation

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Java driven codesign and prototyping of networked embedded systems

Java driven codesign and prototyping of networked embedded s...

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Design Automation conference

作者： J. Fleischmann K. Buchenrieder R. Kress Institute of Electronic Design Automation Technical University Munich Munich Germany Corporate Technology Siemens AG Munich Germany

While the number of embedded systems in consumer electronics is growing dramatically, several trends can be observed which challenge traditional codesign practice: an increasing share of functionality of such systems is implemented in software; flexibility or reconfigurability is added to the list of nonfunctional requirements. Moreover, networked embedded systems are equipped with communication capabilities and can be controlled over networks. In this paper, we present a suitable methodology and a set of tools targeting these novel requirements. JACOP is a codesign environment based on Java and supports specification, co-synthesis and prototyping of networked embedded systems.

关键词： Java Prototypes Embedded system Streaming media hardware Consumer electronics Communication system control Video compression Switches Cryptography

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