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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

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Real time collision detection and avoidance. A case study for design space exploration in HW-SW codesign

Real time collision detection and avoidance. A case study fo...

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international conference on VLSI Design

作者： S.K. Lodha S. Gupta M. Balakrishnan S. Banerjee Department of Computer Science and Engineering Indian Institute of Technology New Delhi India

In this paper we study a collision detection algorithm and partition it into hardware and software parts to enhance the performance of the system and achieve the real time goal (25 frames/sec). We explore the design space to identify various feasible implementations on software, hardware, firmware and mixed platforms. The platforms considered are the Intel's processors and Sun ULTRA1 for software, Motorola DSP56002 for firmware XILINX FPGAs for hardware. The mixed implementations include combinations of the above. A number of implementations discussed establish that factors such as time constraint, pin count and interface requirements strongly influence the design options.

关键词： Computer aided software engineering Space exploration hardware Partitioning algorithms Real time systems Machine vision Image motion analysis Microprogramming Field programmable gate arrays software algorithms

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proceedings OF THE international conference ON COMPUTER COMMUNICATION, 3RD, 1976.

PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON COMPUTER COMM...

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Proc of the Int Conf on Comput Commun, 3rd

proceedings includes 97 papers that reflect the global state-of-the-art in computer communication. The papers are grouped into several sessions dealing with: National and Multi-National Computer Networks and Services, Legal Issues in Computer Communication, Computer Communication system Analysis and Design, Computer Communication Using Satellites, Economic Analysis of Information Technology, Specific Applications of Computer Communications systems, Computer Assisted Conferencing, Management Issues in Computer Networks, Computer Communication system Design, Protocols, synthesis, Performance and Standards, Computer Communication Network Planning, Privacy and Security Issues in Computer Communication, Computer Communication systems: hardware and software, Flow and Congestion Controls in Computer Communication systems, National Policies and Business Development in Computer Communication, Some World Issues in Computer Communication, Datapac, and Computer Architecture.

关键词： Computer networks

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Insect Type MEMS Micro Robot Controlled by CMOS IC of hardware Neural Networks 12

Insect Type MEMS Micro Robot Controlled by CMOS IC of Hardwa...

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12th European conference on the synthesis and Simulation of Living systems: Advances in Artificial Life, ECAL 2013

作者： Takato, M. Yamasaki, S. Takahama, S. Tanida, J. Saito, K. Uchikoba, F. Precision Machinery Engineering Graduate School of Science and Technology Nihon University Japan Dept. of Precision Machinery Engineering Collage of Science and Technology Nihon University Japan

ISBN: (纸本)9780262317092

This paper describes insect type micro robots controlled by a CMOS IC of hardware neural networks. The micro robot is fabricated by the micro electro mechanical systems (MEMS) technology using a silicon wafer, and the actuator is composed of artificial muscle wires on the basis of shape memory alloy. Insect-like walking is achieved by link mechanisms that transform the actuator s rotational motion to locomotive motion. The CMOS IC generates the driving waveform of the micro robot and realizes insect-like walking. The hardware neural networks are built as cell body models and inhibitory synaptic models. The output signal ports of the hardware neural networks are connected to the artificial-muscle-wire-driving circuit. This robot system does not require specialized software programs and A/D converters. The developed neural networks are composed of self-functioning, interconnected plural unit neurons. For proper driving, each neuron in the developed neural network control must be synchronized, as occurs in the neural networks of living organisms. In this study, the motion of the MEMS micro robot is controlled by non-synchronization and anti-phase synchronization driving waveforms. When the nonsynchronization driving waveform is input, the micro robot ceases walking motion, but resumes walking upon receipt of the anti-phase synchronization driving waveform. The sideways, endways, and height dimensions of the fabricated micro robot are 4.0 mm, 2.7 mm and 2.5 mm, respectively. The obtained locomotion speed is 26.4 mm/min and the step width is 0.88 mm. © 2013 proceedings of the 12th European conference on the synthesis and Simulation of Living systems: Advances in Artificial Life, ECAL 2013. All rights reserved.

关键词： Neural networks

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A co-design methodology based on formal specification and high-level estimation 96

A co-design methodology based on formal specification and hi...

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international Workshop on hardware/software codesign (CODES)

作者： C. Carreras J.C. Lopez M.L. Lopez C. Delgado-Kloos N. Martinez L. Sanchez Department Ing. Electrónica ETSIT University of Politecnica de Madrid Madrid Spain Department Ing. Sistemas Telemáticos ETSIT University of Politecnica de Madrid Madrid Spain Department Ingeniería Universidad Carlos III de Madrid Leganes Spain

ISBN: (纸本)9780818672439

This paper presents a methodology for hardware-software co-design. It is based on the formal description technique LOTOS in the specification phase, and on estimation methods at different levels of abstraction in the partitioning phase. The LOTOS specification describes the system as a set of interacting communicating processes. Our HW-SW partitioning algorithm is guided by communications, performance and area estimates and by the suitability of each process for implementation in hardware or software. A partition is evaluated against the design goals and constraints, first using high-level estimates and then if requirements are met, computing estimates at lower levels of abstraction. If the partition fails, the partitioning model is updated with the new, low-level estimates and a new partition is generated. If it succeeds, the resulting hardware and software specifications are synthesized using existing high-level synthesis tools and compilers.

关键词： Formal specifications hardware Phase estimation software performance Control system synthesis Costs Application specific integrated circuits Partitioning algorithms software algorithms software tools

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7th international Workshop on Field-Programmable Logic and Applications, FPL 1997

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7th international Workshop on Field Programmable Logic and Applications, FPL 1997

ISBN: (纸本)3540634657

The proceedings contain 51 papers. The special focus in this conference is on Devices and Architectures. The topics include: Multicontext dynamic reconfiguration and real time probing on a novel mixed signal programmable device with on-chip microprocessor;CAD-oriented FPGA and dedicated CAD system for telecommunications;a three dimensional FPGA architecture, its fabrication, and design tools;extending dynamic circuit switching to meet the challenges of new FPGA architectures;performance evaluation of a full speed PCI initiator and target subsystem using FPGAs;implementation of pipelined multipliers on xilinx FPGAs;the XC6200DS development system;thermal monitoring on FPGAs using ring-oscillators;a reconfigurable approach to low cost media processing;a flexible platform for codesign and dynamic reconfigurable computing research;stream synthesis for a wormhole run-time reconfigurable platform;pipeline morphing and virtual pipelines;parallel graph colouring using FPGAs;run-time compaction of FPGA designs;partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement;a case study of partially evaluated hardware circuits;run-time parameterised circuits for the xilinx XC6200;automatic identification of swappable logic units in XC6200 circuitry;towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic;exploiting reconfigurability through domain-specific systems;technology mapping by binate covering;a new packing, placement and routing tool for FPGA research;technology mapping of heterogeneous LUT-based FPGAs and technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs.

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Keynote talk II: Multiform logical time for Me/Mo-codesign

Keynote talk II: Multiform logical time for Me/Mo-codesign

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ACM and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Robert de Simone Inria Le Chesnay ÃŽle-de-France FR

ISBN: (纸本)9781509027927

There is now a consistent corpus of models and methods for software/hardware codesign (scope of MeMoCoDe). Still, while success is quite established at both ends of the spectrum (High-Level hardware synthesis, and system Engineering), the adoption of such software modeling approach inside mainstream software Engineering communities could easily be improved. This is certainly so because some of the principles of application modeling do not exactly match, or elsewhere do not focus upon the same concerns, as traditional coding style. Putting forth the relevant important concepts for application modeling, while investigating their relevance to traditional engineering experience, is certainly a way to counter confusion. We view the notion of Multiform Logical Time as such a fundamental concept. In a first part of the talk we consider the premises of Multiform Logical Time in Embedded Design (its origin, its relevance at places of design flows); in a second part we introduce a small declarative language to express logical time properties, study its expressiveness and its associated analysis techniques.

关键词： Unified modeling language Embedded systems Semantics Parallel processing Algebra Model checking Collaboration

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YOUFILE: Ontology based system for document smart indexing

YOUFILE: Ontology based system for document smart indexing

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12th World Multi-conference on systemics, Cybernetics and Informatics/14th international conference on Information systems Analysis and synthesis

作者： Mainetti, Luca Paiano, Roberto Bucciero, Alberto Guido, Anna Lisa Sabato, Stefano Santo Capone, Luciano Barchetti, Ugo Pulimeno, Enrico Univ Salento I-73100 Lecce Italy

ISBN: (纸本)9781934272374

The huge amount of files of different types (from photos, personal documents, to accounting or fiscal documents) which everyone stores in his own personal computer or in other hardware device (such as internet virtual space, external hard drives, etc.) risk, with the passing of time, to go lost. The founding idea of the eSCI project (eStore of Captured Information) is just to avoid the accidental loss of files, proposing to develop a web portal which allows the user to safely store his own documents and to retrieve them whenever he wants through a simple internet connection. Within the scope of this research project, the reached objective was double: first to assist the user in the document indexing activity, leading him to define the right keywords able to univocally characterize each file;in this way the user doesn't index the document only though its file name but also providing more precise information about its content. This allows to characterize the document according to a semantic meaning which will make its retrieval easier. At the same time, we would develop a software architecture that should be able to automatically generate the right data entry forms needed to index each particular class of documents, avoiding the expensive activities of the evolutive maintenance of the application. We made use of ontologies to express the real semantic value that each document could hide. simplifying their indexing and retrieval.

关键词： On the fly form generation Ontology Electronic documents ontology and database synchronization Document classification

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An equivalence checker for hardware-dependent embedded system software 13

An equivalence checker for hardware-dependent embedded syste...

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proceedings of the Eleventh ACM/IEEE international conference on Formal Methods and Models for codesign

ISBN: (纸本)9781479909056

This paper presents a novel approach to formally prove the equivalence of low-level hardware-dependent programs. Inspired by hardware verification techniques, a software miter is created that compares the behaviors of two programs, taking into account the interfaces between the software and the hardware environments. Two programs are considered equivalent if they produce the same outputs for the same input assignments and also exhibit the same sequences of interactions with the relevant hardware peripherals. This motivates a hardware-dependent computational model combining a path-oriented program view, as is common in hardware-independent software verification, with a structural hardware representation of the program's computation. Experimental results show the effectiveness of the proposed technique for industrial low-level software in important equivalence checking scenarios such as code porting and automated/manual code transformations.

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Process partitioning for distributed embedded systems 96

Process partitioning for distributed embedded systems

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international Workshop on hardware/software codesign (CODES)

作者： Junwei Hou W. Wolf Department of Electrical Engineering Princeton University Princeton NJ USA

ISBN: (纸本)9780818672439

We present a new technique for partitioning processes in distributed embedded systems. Our heuristic algorithm minimizes both context switch and communication overhead under real-time deadline and process size constraints; it also tries to allocate functions to processors which are well-suited to that function. The algorithm analyzes the sensitivity of the latency of the task graph to changes in vertices hierarchical clustering, splitting and border adjusting. This algorithm can be used for initial partitioning during co-synthesis of distributed embedded systems. synthesis of examples partitioned by our algorithm with implementations synthesized directly from the original example shows that our partitioning algorithm significantly improves the results obtainable by practical co-synthesis algorithms.

关键词： Embedded system Clustering algorithms Partitioning algorithms Embedded computing Data flow computing Flow graphs Switches Algorithm design and analysis Application specific integrated circuits Cost function

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hardware/software partitioning of software binaries: a case study of H.264 decode 05

Hardware/software partitioning of software binaries: a case ...

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proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Greg Stitt Frank Vahid Gordon McGregor Brian Einloth University of California Riverside Freescale Semiconductor

ISBN: (纸本)9781595931610

We describe results of a case study whose intent was to determine whether new techniques for hardware/software partitioning of an application's binary are competitive with partitioning at the C source code level. While such competitiveness has been shown previously for standard benchmark suites involving smaller or unoptimized applications, the case study instead focuses on a complete 16,000-line highly-optimized commercial-grade application, namely an H.264 video decoder. The several month study revealed that binary partitioning was indeed competitive, achieving nearly identical 2.5x speedups as source level partitioning, compared to a standard microprocessor. Furthermore, the study revealed that several simple C-level coding modifications, including pass by value-return, function specialization, algorithmic specialization, hardware-targeted reimplementation, global array elimination, hoisting and sinking of error code, and conversion to explicit control flow, could lead to improved application speedups approaching 7x for both source level and binary level partitioning.

关键词： synthesis binaries H.264 hardware/software partitioning FPGA embedded systems

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