A new codesign compiler, Dash, provides a co-synthesis and co-simulation environment for mixed FPGA/processor architectures. It compiles a C-like description to a solution containing both processors and custom hardwar...
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A new codesign compiler, Dash, provides a co-synthesis and co-simulation environment for mixed FPGA/processor architectures. It compiles a C-like description to a solution containing both processors and custom hardware, and allows the descriptions of FPGA-based processors to be heavily parametrized. The user may add instructions to the processors, and the Dash software architecture allows the user to add facilities for targeting these extra instructions to the compiler. This system is being used to design a number of case studies, and a single-chip codesign of an Internet video game is used to illustrate the design flow.
Embedded systems typically include reactive and transformative functions, often described in different languages and semantics which are well introduced in the various application fields. A large part of the system fu...
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ISBN:
(纸本)0769501524
Embedded systems typically include reactive and transformative functions, often described in different languages and semantics which are well introduced in the various application fields. A large part of the system functionality and components is reused from previous designs including legacy code. There is little hope that a single language will replace this heterogeneous set of languages. A hardware/softwarecodesign process must be able to bridge the semantic differences for verification and synthesis and should accept limited knowledge of system properties. This paper presents the SP1 model which is based on intervals of system properties and is specifically targeted to cosynthesis. This model is the basis of a workbench which is currently under construction in an international cooperation.
In hardware are - softwarecodesign paradigm often a performance estimation of the system is needed for hardware are - software partitioning. The tremendous growth of application specific embedded systems necessitate ...
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ISBN:
(纸本)0769500137
In hardware are - softwarecodesign paradigm often a performance estimation of the system is needed for hardware are - software partitioning. The tremendous growth of application specific embedded systems necessitate high level system design tools for rapid prototyping. This work involves design of a language Sim-nML,which will be the base for a high level system design environment. The language is simple, elegant and powerful enough to express the behavior of the processor at instruction level. This language is used as the base for a whole set of tools such as assembler;disassembler and simulator generator: As a pall of this,cork, Ire implemented an instruction set simulator generator which takes Sim-nML description of the processor as input and produces C++ code for performance simulator I the envisage the use of the generated simulator for cycle based analysis of the processor and for performance estimation of the system. This work is primarily an extension of nML[2] language.
The architecture of systems tailored for a specific application frequently requires cooperation among hardware and software components. The design of these systems is typically a compromise among a number of factors: ...
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ISBN:
(纸本)3540660933
The architecture of systems tailored for a specific application frequently requires cooperation among hardware and software components. The design of these systems is typically a compromise among a number of factors: cost, performance, size, development time, power consumption, etc. To cope with increasing possibilities offered by nowadays integration technology and steady demanding of shorter time-to-market, a comprehensive strategy aiming at gathering all the involved aspects of the design is becoming mandatory This new discipline, called codesign, considers in a concurrent manner all the activities involved in the design of a mixed hw/sw dedicated system: capturing of design specification and requirements, mapping of the design onto hardware and software domains, systemsynthesis and design verification. The paper introduces the key factors involved in the design of an embedded system, together with a description on how codesign is overcoming such problems, opening the way to a new generation of CAD frameworks supporting system-level design.
With the growth of system on a chip (SoC), the functionality of analog components must also be considered in the design process. This paper describes some of the design implementation partitioning issues and experienc...
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This paper presents a genetic algorithm to solve the systemsynthesis problem of mapping a time constrained single-rate system specification onto a given heterogeneous architecture which may contain irregular intercon...
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This paper presents a genetic algorithm to solve the systemsynthesis problem of mapping a time constrained single-rate system specification onto a given heterogeneous architecture which may contain irregular interconnection structures. The synthesis is performed under memory constraints, that is, the algorithm takes into account the memory size of processors and the size of interface buffers of communication links, and in particular the complicated interplay of these. The presented algorithm is implemented as part of the LYCOS cosynthesissystem.
This paper presents an approach for linking design and verification environments in the context of hardware/softwarecodesign of complex systems, based on refinement steps of the system implementation. We describe the...
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We propose a systemsynthesis method which bridges the gap between a highly abstract functional model and an efficient hardware or software implementation. The functional model is based on a formal semantics and the s...
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We propose a systemsynthesis method which bridges the gap between a highly abstract functional model and an efficient hardware or software implementation. The functional model is based on a formal semantics and the synchrony hypothesis. However, the use of skeletons in conjunction with a proper computational model structures the system description into three layers, the system layer, the skeleton layer, and the elementary layer. The synthesis process takes advantage of this structure and uses a different technique for each layer: (a) connection of components and processes at the system layer;(b) template based generation of compound entities possibly containing state information, memory, and complex control at the skeleton layer;this layer also determines the communication and timing behaviour;(c) direct translation into combinatorial functions at the elementary layer. Thus, without compromising the formal properties of the abstract system model we provide an efficient synthesis method.
With the growth of system on a Chip (SoC), the functionality of analog components must also be considered in the design process. This paper describes some of the design implementation partitioning issues and experienc...
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With the growth of system on a Chip (SoC), the functionality of analog components must also be considered in the design process. This paper describes some of the design implementation partitioning issues and experiences using analog and digital techniques for embedded systems. To achieve a quick turn around for new embedded system development, a design methodology was extended for analog codesign based on the specify-explore-refine paradigm and system-level design methodology. Many system-level issues were addressed including hardware/softwarecodesign trade-offs.
The important aspects on system-level design based on industrial experiences are outlined. The issues discussed relate to two key characteristics of early system design, exploration and incompleteness. It is argued th...
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The important aspects on system-level design based on industrial experiences are outlined. The issues discussed relate to two key characteristics of early system design, exploration and incompleteness. It is argued that system-level methods and tools must deal with these key factors.
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