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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

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A Methodology for Generating Application-Specific Heterogeneous Processor Arrays

A Methodology for Generating Application-Specific Heterogene...

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Annual Hawaii international conference on system Sciences (HICSS)

作者： S. Craven C. Patterson P. Athanas Virginia Polytechnic Institute and State University USA

hardware designers are increasingly turning to Single Chip Multi-Processors to achieve power and throughput goals. To further increase performance for a specific application the chip’s array of processors can be tailored to their program, creating an application-specific multiprocessor. While much hardware/software codesign research has been conducted on optimizing heterogeneous processing arrays, shortcomings exist in design scalability, simulation, verification, rapid prototyping, and the requirement of specialized skill sets. To address these deficiencies, a design methodology is proposed targeting signal processing applications that maps a parallelized C program onto a homogenous array of processors linked by simple point-to-point connections. By individually optimizing each processor for its specific program the performance of the array is increased, while the common basic interface between processors eases optimization, implementation, debugging, and verification.

关键词： hardware Application software Turning Throughput Design optimization Scalability software prototyping Virtual prototyping Design methodology Array signal processing

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Optimized software mapping for advanced driver assistance systems

Optimized software mapping for advanced driver assistance sy...

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7th IEEE international Symposium on Industrial Embedded systems, SIES 2012

作者： Schönwald, Timo Viehl, Alexander Bringmann, Oliver Rosenstiel, Wolfgang FZI Forschungszentrum Informatik Haid-und-Neu-Str. 10-14 76131 Karlsruhe Germany Universität Tübingen Sand 13 72076 Tübingen Germany

ISBN: (纸本)9781467326841

In this paper, we present a novel approach for automated latency-optimized mapping of processes onto cores of NoC-based MPSoCs. During the mapping determination, the routing algorithm for packet-based communication is taken into account. The basic idea of the presented approach is the reduction of communication conflicts on the communication network links for reducing the overall communication latency and hence for increasing the total system performance. The presented approach is based on the idea of force-directed scheduling (FDS) from high-level synthesis. It maps the problem of conflict avoidance to forces for deriving an optimized process mapping. We present results obtained from two advanced driver assistance systems (ADAS), a traffic sign recognition and a depth map computation for a stereo camera system used for object recognition. As hardware platform we used a Tilera TILEPro64 processor system. © 2012 IEEE.

关键词： Mapping

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The Integration and Testing Procedures for the AcubeSAT Nanosatellite's software 20

The Integration and Testing Procedures for the AcubeSAT Nano...

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20th international conference on synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024

作者： Keremidis, Antonios Tzelepis, Stylianos Hatzopoulos, Alkis National Technical University of Athens Greece SpaceDot Greece Aristotle University of Thessaloniki Greece AUTh Electronics Lab Dept. of Electrical and Computer Eng Greece

ISBN: (纸本)9798350351927

The AcubeSAT space mission, a collaborative effort within the Fly Your Satellite! 3 program of the European Space Agency (ESA) Education Office and SpaceDot, features unique payload requirements aimed at exploring the effects of radiation and microgravity on eukaryotic cells in Low Earth Orbit (LEO). To address these specialized needs, custom Printed Circuit Board (PCB)s were developed, bypassing off-the-shelf solutions for greater efficiency of the mission and cost-effectiveness. However, this decision introduced a notable challenge: the development of complex system software to ensure the successful execution of all mission phases and the secure transmission of scientific data back to Earth. In this paper, we report on the status of the development and validation processes for the satellite software in its current state, on custom hardware to ensure mission success. © 2024 IEEE.

关键词： Integration testing

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SIGNAL PROCESSING hardware AND software APPLIED TO THE DEVELOPMENT OF A REAL-TIME INFRARED MISSION SIMULATION TEST CAPABILITY

SIGNAL PROCESSING HARDWARE AND SOFTWARE APPLIED TO THE DEVEL...

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conference on Smart Focal Plane Arrays and Focal Plane Array Testing

作者： FUGERER, RH LOWRY, HS HERVIG, DJ HOLT, LL MICRO CRAFT TECHNOL INC AEDC OPERATARNOLD AFBTN 37389

ISBN: (纸本)0819418277

The Arnold Engineering Development Center (AEDC) Scene Generation Test Capability (SGTC) program has completed the development of a laser based Direct Write Scene Generation (DWSG) facility that provides dynamic mission simulation testing for infrared (IR) Focal Plane Array (FPAs) and their associated signal processing electronics. The AEDC DWSG Focal Plane Array Test Capability includes lasers operating at 0.514, 1.06, 5.4, or 10.6 micrometers , and Acousto-Optic Deflectors (AODs) which modulate the laser beam position and amplitude. Complex Radio Frequency (RF) electronics control each AOD by providing multi-frequency inputs. These inputs produce a highly accurate and independent multi-beam deflection, or `rake', that is swept across the FPA sensor under test. Each RF amplitude input to an AOD translates into an accurate and independent beam intensity in the rake. Issues such as scene fidelity, sensor frame rates, scenario length, and real-time laser beam position adjustments require RF control electronics that employ the use of advanced analog and digital signal processing techniques and designs. By implementing flexible system architectures in the electronics, the overall capability of the DWSG to adapt to emerging test requirements is greatly enhanced. Presented in this paper is an overview of the signal processing methodology and designs required to handle the DWSG requirement. Further, electronic design techniques that enabled the system to be implemented within program cost constraints will also be presented. These electronic designs include a broad range of disciplines including digital signal processing hardware and software, programmable logic implementations, and advanced techniques for high fidelity RF synthesis, switching, and amplitude control. Techniques for validating electronic performance will also be presented along with data acquired using those techniques.

关键词： SCENE INFRARED FPA SENSOR ANALOG DIGITAL RF ACOUSTOOPTIC DEFLECTOR DIGITAL SYNTHESIZER FRAME

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Remote detection of unauthorized activity via spectral analysis: work-in-progress 17

Remote detection of unauthorized activity via spectral analy...

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proceedings of the Twelfth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis Companion

作者： Fatih Karabacak Umit Ogras Sule Ozev Arizona State University

ISBN: (纸本)9781450351850

Unauthorized hardware or firmware modifications, known as trojans, can steal information, drain the battery, or damage IoT devices. This paper presents a stand-off self-referencing technique for detecting unauthorized activity. The proposed technique processes involuntary electromagnetic emissions on a separate hardware, which is physically decoupled from the device under test. When the device enter the test mode, it runs a predefined application repetitively with a fixed period. The periodicity ensures that the spectral electromagnetic power of the test application concentrates at known frequencies, leaving the remaining frequencies within the operation bandwidth at the noise level. Any deviations from the noise level for these unoccupied frequency locations indicates the presence of unknown (unauthorized) activity. Experiments based on hardware measurements show that the proposed technique achieves close to 100% detection accuracy at up to 120 cm distance.

关键词： EM emission hardware/firmware trojan detection IoT security

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A concept of a hardware design environment with the functional language elixir: work-in-progress 19

A concept of a hardware design environment with the function...

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proceedings of the international conference on hardware/software codesign and system synthesis Companion

作者： Hideki Takase Kentaro Matsui Yoshihiro Ueno Masakazu Mori Yuki Hisae Susumu Yamazaki Kyoto University Sakyo-ku Kyoto Japan Delight Systems Co. Ltd. Chuo-ku Fukuoka Japan Karabiner Technology Inc. Chuo-ku Fukuoka Japan The University of Kitakyushu Wakamatsu-ku Kitakushu Japan

ISBN: (纸本)9781450369237

The functional language Elixir is designed to be effective for the application. One of the most considerable feature of Elixir is that it is easy to realize the parallel processing with the standard library, such as Flow. In this paper, we study a design environment for hardware circuits using Elixir as a design language. We propose a synthesize flow for data flow hardware on the FPGA from the native Elixir code. Our method synthesizes functional equivalence circuits from the description of Enum and Flow in Elixir, which are libraries for direct manipulation and parallel processing of data collection in Elixir. Data flow is implemented base on the pipeline operator |> which connects the processing relation of the function by the data processing order. To realize a hardware design environment by Elixir, this paper shares current status of our implementation.

关键词： functional language elixir high-level synthesis

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Agile design of DCT circuit on soft CGRA

Agile design of DCT circuit on soft CGRA

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2021 international conference on High Performance Computing and Communication, HPCCE 2021

作者： Li, Dongping Luo, Guojie Yan, Wei School of Software and Microelectronics Peking Univ./City Beijing 24 Jinyuan Road Daxing District Beijing100000 China Center for Energy-efficient Computing and Applications Peking Univ./City Beijing 5 Summer Palace Road Haidian District Beijing100000 China

ISBN: (数字)9781510652019

ISBN: (纸本)9781510652002

High-level synthesis technology is a technology for circuit design using high-level languages such as C, C++, or system C. This design method is suitable for algorithm engineers to implement calculation prototypes and is not suitable for hardware engineers to design circuits from the register transfer level. In addition, from the perspective of agile development and code reuse, C, C++, and system C are far from another hardware description language, Chisel. However, there are relatively few electronic design automation tools for Chisel, so we propose a circuit design flow based on CGRA hardware, in which Chisel designs the PE unit of CGRA. However, Chisel has few electronic design automation tools, so a circuit design flow based on CGRA is proposed. Dedicated data flow graph generation tools and typical coarse-grained reconfigurable arrays are implemented for this design flow. This article describes a design process based on CGRA and compares the design process with HLS through the DCT circuit design process. Through the experimental comparison of the two circuit implementation processes, it is found that, first of all, the correctness of the CGRA-based design process and the availability of data flow diagram generation tools. Secondly, from a design point of view, the use of Chisel will increase the overall development speed and increase the reusability of design files. Finally, from the perspective of toolchains, part of the tools in the new design process uses open-source toolchains, which reduces the cost of using toolchains and promotes the development of toolchains to a certain extent. © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.

关键词： Data flow graphs

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hardware/software codesign methodology for fuzzy controller implementation

Hardware/software codesign methodology for fuzzy controller ...

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IEEE international conference on Fuzzy systems (FUZZ-IEEE)

作者： A. Cabrera S. Sanchez-Solano R. Senhadji A. Barriga C.J. Jimenez Departmento Automática y Computación. Facultad de Ingenierí a Eléctrica Instituto Superior Politécnico José Antonio Echevarría Cuba Instituto de Microelectrónica de Sevilla óIMSE CNM Seville Spain

Describes a HW/SW codesign methodology for the implementation of fuzzy controllers on a platform composed of a general-purpose microcontroller and specific processing elements implemented on FPGAs or ASICs. The different phases of the methodology, as well as the CAD tools used in each design stage, are presented, with emphasis on the fuzzy system development environment Xfuzzy. Also included is a practical application of the described methodology for the development of a fuzzy controller for a dosage system.

关键词： hardware Fuzzy control Fuzzy systems Control systems Computer architecture Microcontrollers Fuzzy logic Field programmable gate arrays Design automation Functional programming

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Strongly polynomial-time algorithm for over-constraint resolution: efficient debugging of timing constraint violations

Strongly polynomial-time algorithm for over-constraint resol...

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international Workshop on hardware/software codesign (CODES)

作者： A. Dasdan Advanced Technology Group Synopsys Inc. Mountain View CA USA

A system of binary linear constraints or difference constraints (SDC) contains a set of variables that are constrained by a set of unary or binary linear inequalities. In such diverse applications as scheduling, interface timing verification, real-time systems, multimedia systems, layout compaction, and constraint satisfaction, SDCs have successfully been used to model systems of both temporal and spatial constraints. Formally, SDCs are modeled by weighted, directed (constraint) graphs. The consistency of an SDC means that there is at least one instantiation of its variables that satisfies all its constraints. It is well known that the absence of positive cycles in a graph implies the consistency of the corresponding SDC, so the consistency can be decided in strongly polynomial time. If a SDC is found to be inconsistent, it has to be repaired to make it consistent. This task is equivalent to removing positive cycles from the corresponding graph. All the previous algorithms for this task take time proportional to the number of positive cycles in the graph, which can grow exponentially. In this paper, we propose a strongly polynomial-time algorithm, i.e., an algorithm whose time complexity is polynomial in the size of the graph. Our algorithm takes in a graph and returns a list of edges and the changes in their weights to remove all the positive cycles from the graph. We experimentally quantify the length of the edge list and the running time of the algorithm on large benchmark graphs. We show that both are very small, so our algorithm is practical.

关键词： Polynomials Timing Permission Debugging Real time systems Multimedia systems Compaction Lakes High level synthesis Performance gain

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Tutorial: Large-Scale Spiking Neuromorphic Architecture Exploration using SANA-FE

Tutorial: Large-Scale Spiking Neuromorphic Architecture Expl...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： James A. Boyle Mark Plagge Suma G. Cardwell Frances S. Chanc Andreas Gerstlauer The University of Texas at Austin Texas USA Sandia National Laboratories New Mexico USA

ISBN: (数字)9798350356397

ISBN: (纸本)9798350356403

Neuromorphic computing uses brain-inspired concepts to accelerate and efficiently execute a wide range of applications, such as mimicking biological circuits, solving NPhard optimization problems and accelerating machine learning at the edge. In particular, neuromorphic architectures to efficiently execute Spiking Neural Networks (SNNs) have gained popularity. SNNs extend artificial neural networks (ANNs) by encoding information in time as either rates or delays between spiking events, shared between neurons via their weighted connections. SNN-based platforms are event-driven, resulting in naturally sparse, noise-tolerant and power-efficient computation. In this tutorial, we present the state-of-the-art in scalable digital and analog spiking neuromorphic system architectures, and discuss current research trends within the neuromorphic architecture field at the system level. We further introduce our SANA-FE tool for Simulation of Advanced Neuromorphic Architectures for Fast Exploration, which has been developed as part of a collaboration between the University of Texas at Austin and Sandia National Laboratories. SANA-FE allows for modeling and performance-power prediction of different spiking hardware architectures executing SNN applications to support rapid, early system-level design-space exploration, hardware-aware application development and system architecture co-design. The tutorial includes a hands-on component in which SANA-FE’s capabilities are demonstrated and used to perform system design and application mapping case studies.

关键词： Neuromorphic engineering Neurons systems architecture Computer architecture Tutorials Spiking neural networks Predictive models Market research system analysis and design Optimization

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