The proceedings contain 433 papers. The topics discussed include: a fully integrated 2 GHz frequency synthesizer;new circuit techniques based on a high performance frequency-TC-voltage converter;an enhanced frequency ...
ISBN:
(纸本)0780356829
The proceedings contain 433 papers. The topics discussed include: a fully integrated 2 GHz frequency synthesizer;new circuit techniques based on a high performance frequency-TC-voltage converter;an enhanced frequency synthesizer using an analog dual input accumulator;automatic architecture evaluation for hardware/softwarecodesign;low-voltage linear OTA with rail-to-rail differential mode input signal capability;low-power implementation of a residue-to-weighted conversion unit for a 5-moduli RNS;an improved nonlinear analysis and design method of microstrip oscillators based on modem CAD techniques;feedforward ANC system using adaptive FIR filters with on-line secondary path identification;a design procedure for 2-channel mixed analog and digital filter banks for A/D conversion using minimax optimization;controlling chaotic nonlinear dynamical systems;user choices for efficient 3D motion and shape extraction from orthographic projections;and code acquisition in CDMA communication system with fictitious pilot signals.
The proceedings contain 433 papers. The topics discussed include: a fully integrated 2 GHz frequency synthesizer;new circuit techniques based on a high performance frequency-TC-voltage converter;an enhanced frequency ...
ISBN:
(纸本)0780356829
The proceedings contain 433 papers. The topics discussed include: a fully integrated 2 GHz frequency synthesizer;new circuit techniques based on a high performance frequency-TC-voltage converter;an enhanced frequency synthesizer using an analog dual input accumulator;automatic architecture evaluation for hardware/softwarecodesign;low-voltage linear OTA with rail-to-rail differential mode input signal capability;low-power implementation of a residue-to-weighted conversion unit for a 5-moduli RNS;an improved nonlinear analysis and design method of microstrip oscillators based on modem CAD techniques;feedforward ANC system using adaptive FIR filters with on-line secondary path identification;a design procedure for 2-channel mixed analog and digital filter banks for A/D conversion using minimax optimization;controlling chaotic nonlinear dynamical systems;user choices for efficient 3D motion and shape extraction from orthographic projections;and code acquisition in CDMA communication system with fictitious pilot signals.
We propose a systemsynthesis method which bridges the gap between a highly abstract functional model and an efficient hardware or software implementation. The functional model is based on a formal semantics and the s...
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We propose a systemsynthesis method which bridges the gap between a highly abstract functional model and an efficient hardware or software implementation. The functional model is based on a formal semantics and the synchrony hypothesis. However, the use of skeletons in conjunction with a proper computational model structures the system description into three layers, the system layer, the skeleton layer, and the elementary layer. The synthesis process takes advantage of this structure and uses a different technique for each layer: (a) connection of components, and processes at the system layer; (b) template based generation of compound entities possibly containing state information, memory, and complex control at the skeleton layer; this layer also determines the communication and timing behaviour; (c) direct translation into combinatorial functions at the elementary layer. Thus, without compromising the formal properties of the abstract system model we provide an efficient synthesis method.
Task structuring is the process of determining the individual tasks of a system, leading to the system's description as a task graph. This paper shows that RADHA-RATAN, our rate derivation algorithms, can be used ...
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Task structuring is the process of determining the individual tasks of a system, leading to the system's description as a task graph. This paper shows that RADHA-RATAN, our rate derivation algorithms, can be used to validate various tradeoffs made during task structuring, making this step timing aware. We show how RADHA-RATAN enables construction of a high-level timing model of the system leading to a process timing simulation of the entire system. An interesting aspect of process timing simulation is that it provides the ability to observe system level timing behavior based on timing requirements and analysis before an implementation of the tasks has been carried out. Based on task structuring and process timing simulation we propose a codesign methodology by which a system designer can gain insight into the system's timing performance. This approach enables the designer to reduce expensive timing driven design iterations. We have implemented this methodology in the RADHA-RATAN framework. We illustrate its application by an example.
This paper presents a genetic algorithm to solve the systemsynthesis problem of mapping a time constrained single-rate system specification onto a given heterogeneous architecture which may contain irregular intercon...
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This paper presents a genetic algorithm to solve the systemsynthesis problem of mapping a time constrained single-rate system specification onto a given heterogeneous architecture which may contain irregular interconnection structures. The synthesis is performed under memory constraints, that is, the algorithm takes into account the memory size of processors and the size of interface buffers of communication links, and in particular the complicated interplay of these. The presented algorithm is implemented as part of the LY-COS cosynthesissystem.
Reducing power consumption is critical in many system designs. Dynamic power management is an effective approach to decrease power without significantly degrading performance. Power management decisions can be impleme...
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Reducing power consumption is critical in many system designs. Dynamic power management is an effective approach to decrease power without significantly degrading performance. Power management decisions can be implemented in either hardware or software. A recent trend on personal computers is to use software to change hardware power states. This paper presents a software architecture that allows system designers to investigate power management algorithms in a systematic fashion through a template. The architecture exploits the Advanced Configuration and Power Interface (ACPI), a standard for hardware and software. We implement two algorithms for controlling the power states of a hard disk on a personal computer running Microsoft Windows. By measuring the current feeding the hard disk, we show that the algorithms can save up to 25% more energy than the Windows power manager. Our work has two major contributions: a template for software-controlled power management and experimental comparisons of management algorithms for a hard disk.
At the system level design of a real-time embedded system, a major issue is to identify from alternative architectures the best one which satisfies the timing constraints. This issue leads to the need of a metric that...
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At the system level design of a real-time embedded system, a major issue is to identify from alternative architectures the best one which satisfies the timing constraints. This issue leads to the need of a metric that is capable of evaluating the overall system timing performance. Some of the previous work in the related areas focus on predicting the system's timing performance based on a fixed computation time model. These approaches are often too pessimistic. Those that do consider varying computation times for each task are only concerned with the timing behavior of each individual task. Such predictions may not properly capture the timing behavior of the entire system. In this paper, we introduce a metric that reflects the overall timing behavior of RTES. Applying this metric allows a comprehensive comparison of alternative system level designs.
作者：
J. ZhuD.D. GajskiCECS
Information and Computer Science University of California Irvine CA USA
In this paper, we develop a formal framework to widen the scope of retargetable compilation. The goal is achieved by the unification of architectural models for both the processor architecture and the ASIC architectur...
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In this paper, we develop a formal framework to widen the scope of retargetable compilation. The goal is achieved by the unification of architectural models for both the processor architecture and the ASIC architecture. This framework enables the unified treatment of code generation and behavioral synthesis, and is being used in our experimental codesign environment to drive system-on-a-chip synthesis from an object oriented language.
Several models and algorithms have been proposed in the past to generate HW/SW components for system-level designs. However, they were focused on a single designer who had a throughout knowledge of the design. In othe...
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Several models and algorithms have been proposed in the past to generate HW/SW components for system-level designs. However, they were focused on a single designer who had a throughout knowledge of the design. In other words, the decision trade-offs were simplified to a stand-alone developer who did not have to consider individual skills, concurrent development for portions of the design, risk analysis for time-to-market development, nor team load and assignment. In this paper, we propose a design management approach associated with a partitioning methodology to deal with the concurrent design problems of system-level specifications. This methodology allows one to incorporate the uncertainties related to development at the very early stages of the design, and to follow up during the development of a final product.
A known problem in the area of hardware/softwarecodesign is the selection of the proper interface between the different parts of the design. This paper presents a technique which eases the selection by combining diff...
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A known problem in the area of hardware/softwarecodesign is the selection of the proper interface between the different parts of the design. This paper presents a technique which eases the selection by combining different synthesis techniques together with rapid prototyping. Application field of the technique is the design of communication systems where C and VHDL are generated from a specification given in SDL. For the VHDL area, high-level synthesis is used to synthesized a behavioural description.
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