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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

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A High-Speed, Area-Optimized, ROM-Less (Co)Sine Wave synthesis Accelerator 16

A High-Speed, Area-Optimized, ROM-Less (Co)Sine Wave Synthes...

引用

16th international Symposium on Electronics and Telecommunications, ISETC 2024

作者： Stoica, Florentina-Giulia Calinescu, Alex Enachescu, Marius Electronic Devices Circuits and Architectures University Politehnica of Bucharest Faculty of Electronics Telecommunications and Information Technology Bucharest Romania

ISBN: (纸本)9798350390865

Sine and cosine wave synthesis is utilized for generating sinusoidal-alike values in the digital domain. While this task is handled through software, dedicated hardware like Direct Digital synthesis (DDS) is also available. However, both methods rely on memory resources, such as look-up tables and Read-Only Memories (ROMs), which face latency limitations related to additional memory access times on top of additional Si area. With the advent of real-time arithmetic for sine wave approximation, this paper presents an all-in-one digital module that employs iterative multiply-accumulate (MAC) operations for sine and cosine synthesis, ready to be integrated in systems-on-Chip (SoCs), Field Programmable Gate Arrays (FPGAs), or even standalone ASICs. Compared to ROM-less solutions like Taylor approximation, the proposed architecture achieves 80.80% lower resource utilization, 80.39% reduced propagation delay, and 36.66% higher accuracy in sine and cosine wave approximation, both operating as 32-bit systems with one sample per clock cycle. © 2024 IEEE.

关键词： system-on-chip

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The Integration and Testing Procedures for the AcubeSAT Nanosatellite's software 20

The Integration and Testing Procedures for the AcubeSAT Nano...

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20th international conference on synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024

作者： Keremidis, Antonios Tzelepis, Stylianos Hatzopoulos, Alkis National Technical University of Athens Greece SpaceDot Greece Aristotle University of Thessaloniki Greece AUTh Electronics Lab Dept. of Electrical and Computer Eng Greece

ISBN: (纸本)9798350351927

The AcubeSAT space mission, a collaborative effort within the Fly Your Satellite! 3 program of the European Space Agency (ESA) Education Office and SpaceDot, features unique payload requirements aimed at exploring the effects of radiation and microgravity on eukaryotic cells in Low Earth Orbit (LEO). To address these specialized needs, custom Printed Circuit Board (PCB)s were developed, bypassing off-the-shelf solutions for greater efficiency of the mission and cost-effectiveness. However, this decision introduced a notable challenge: the development of complex system software to ensure the successful execution of all mission phases and the secure transmission of scientific data back to Earth. In this paper, we report on the status of the development and validation processes for the satellite software in its current state, on custom hardware to ensure mission success. © 2024 IEEE.

关键词： Integration testing

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Towards a multi-formalism framework for architectural synthesis: the ASAR project 94

Towards a multi-formalism framework for architectural synthe...

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proceedings of the 3rd international workshop on hardware/software co-design

作者： M. Auguin M. Belhadj J. benzakki C. Carrière G. Durrieu Th. Gautier M. Israël P. Le Guernic M. Lemaître E. Martin P. Quinton L. Rideau F. Rousseau O. Sentieys I3S IRISA LIVE CERT-Onera IRISA-INRIA LISTI IRISA-CNRS INRIA-Sophia LASTI

This paper describes a research project - named ASAR - grouping together six french research teams, oriented towards architectural and system synthesis. A main concern of this project is hardware/software codesign and...

ISBN: (纸本)9780818663154

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Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design 05

Service dependency graph: an efficient model for hardware/so...

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proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Adriano Sarmento Lobna Kriaa Arnaud Grasset Mohamed-Wassim Youssef Aimen Bouchhima Frederic Rousseau Wander Cesario Ahmed Amine Jerraya TIMA Laboratory CEDEX France

ISBN: (纸本)9781595931610

Complex systems-on-chip are designed by interconnecting pre-designed hardware (HW) and software (SW) components. During the design cycle, a global model of the SoC may be composed of HW and SW models at different abstraction levels. Designing HW/SW interfaces to interconnect SoC components is a source of design bottlenecks. This paper describes a service-based model enabling systematic design and co-simulation of HW/SW interfaces for SoC design. This model, called Service dependency graph (SDG) allows modeling of complex and application-specific interfaces. We present also a model generator that can automatically build HW/SW interfaces based on service and resource requirements described by the SDG. This approach has been applied successfully on the design of an MPEG-4 encoder. Additionally the SDG seems to be an excellent intermediate representation for the design automation of HW/SW interfaces.

关键词： service-based model systems-on-chip hardware/software interfaces interface design automation

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Representation of algorithms for schematic synthesis of radio engineering devices in the knowledge base of the expert system

Representation of algorithms for schematic synthesis of radi...

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2020 international conference on Engineering Management of Communication and Technology, EMCTECH 2020

作者： Dolin, G.A. Kudryashova, A.Y. Frisk, V.V. Shakin, V.N. Moscow Technical University of Communications and Informatics Moscow Russia

ISBN: (数字)9781665404488

ISBN: (纸本)9780738130743

Creating a new generation of radio engineering devices requires continuous improvement of centers and computer-aided design systems. Moreover, the hardware design itself is currently impossible to imagine without the widespread use of CAD systems at various levels, including end-to-end. To do this, you need to automate the initial design - circuit synthesis. It is proposed to use object-oriented and production expert systems. The generalized model of RTU synthesis is proposed, which is an ordered sequence of necessary actions of the designer, allowing, depending on the specific design task, to achieve the goal. The algorithm for synthesizing the RTU structure has been developed that provides generation and finding a technical solution that satisfies the technical requirements. The proposed basic rules of generation, transformation, and selection of the synthesized structures of the RED. The main design procedures for the initial stages of RED design and the composition of software tools necessary for the effective use of expert knowledge are defined. The basic principles of dialog interaction with the designer in the formation of the expert knowledge base are formulated. The stages, sequence of actions and procedure for presenting information to the expert when working with the subsystem for identifying expert design knowledge are defined. © ©2020 IEEE.

关键词： Solid modeling Task analysis Computational modeling Object oriented modeling Standards Mathematical model Integrated circuit modeling

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Novel architecture for loop acceleration: a case study 05

Novel architecture for loop acceleration: a case study

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proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Seng Lin Shee Sri Parameswaran Newton Cheung University of New South Wales Sydney Australia

ISBN: (纸本)9781595931610

In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this architecture. To illustrate the advantages of this approach, we investigate a JPEG encoding algorithm and accelerate one of its loop by implementing it in a coprocessor. We contrast the acceleration by implementing the critical segment as two different coprocessors and a set of customized instructions. The two different coprocessor approaches are: a high-level synthesis (HLS) approach; and a custom coprocessor approach. The HLS approach provides a faster method of generating coprocessors. We show that a loop performance improvement of 2.57x is achieved using the custom coprocessor approach, compared to 1.58x for the HLS approach and 1.33x for the customized instruction approach compared with just the main processor. Respective energy savings within the loop are 57%, 28% and 19%.

关键词： ASIP architecture coprocessor latency hiding hardware/software partitioning loop optimization tightly coupled loop acceleration loop pipelining

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Tutorial: Large-Scale Spiking Neuromorphic Architecture Exploration using SANA-FE

Tutorial: Large-Scale Spiking Neuromorphic Architecture Expl...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： James A. Boyle Mark Plagge Suma G. Cardwell Frances S. Chanc Andreas Gerstlauer The University of Texas at Austin Texas USA Sandia National Laboratories New Mexico USA

ISBN: (数字)9798350356397

ISBN: (纸本)9798350356403

Neuromorphic computing uses brain-inspired concepts to accelerate and efficiently execute a wide range of applications, such as mimicking biological circuits, solving NPhard optimization problems and accelerating machine learning at the edge. In particular, neuromorphic architectures to efficiently execute Spiking Neural Networks (SNNs) have gained popularity. SNNs extend artificial neural networks (ANNs) by encoding information in time as either rates or delays between spiking events, shared between neurons via their weighted connections. SNN-based platforms are event-driven, resulting in naturally sparse, noise-tolerant and power-efficient computation. In this tutorial, we present the state-of-the-art in scalable digital and analog spiking neuromorphic system architectures, and discuss current research trends within the neuromorphic architecture field at the system level. We further introduce our SANA-FE tool for Simulation of Advanced Neuromorphic Architectures for Fast Exploration, which has been developed as part of a collaboration between the University of Texas at Austin and Sandia National Laboratories. SANA-FE allows for modeling and performance-power prediction of different spiking hardware architectures executing SNN applications to support rapid, early system-level design-space exploration, hardware-aware application development and system architecture co-design. The tutorial includes a hands-on component in which SANA-FE’s capabilities are demonstrated and used to perform system design and application mapping case studies.

关键词： Neuromorphic engineering Neurons systems architecture Computer architecture Tutorials Spiking neural networks Predictive models Market research system analysis and design Optimization

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Managing complexity in heterogeneous system specification, simulation, and synthesis

Managing complexity in heterogeneous system specification, s...

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international conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： A. Kalavade J.L. Pino E.A. Lee Dept. of Electr. Eng. & Comput. Sci. California Univ. Berkeley CA USA Department of Electrical Engineering and Computer Sciences University of California Berkeley CA USA

system-level design is characterized by a behavioral specification and heterogeneous hardware/software implementations. Exploring the design space is essential for good design. Specifying and managing complex design flows, tracking dependencies and tool invocations, and maintaining consistency of design data and flows are key issues that enable efficient design space exploration. In order to manage the complexity of this design process, an infrastructure that manages these issues, transparent to the user, is presented. These concepts have been implemented in the Ptolemy environment within a framework called DesignMaker. An example design flow for multiprocessor synthesis is presented in some detail to illustrate the features of DesignMaker. The end objective of the framework is to facilitate a flexible system-level codesign assistant.

关键词： hardware Space exploration system-level design Process design Computational modeling Embedded system Control systems Telecommunication control software tools Computer simulation

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A Petri net based approach for performing the initial allocation in hardware/software codesign

A Petri net based approach for performing the initial alloca...

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IEEE international conference on systems, Man and Cybernetics

作者： P. Maciel E. Barros W. Rosenstiel Departmento de Informática CEP Universitdade de Pernambuco Recife Brazil Fakultaet fuer Informatik Universitaet Tuebingen Tubingen Germany

This work presents a method of hardware/software partitioning considering multiple software components. The proposed method uses Petri nets as a common formalism to perform quantitative and qualitative analysis. The use of Petri net permits one to use a specification nondependent partitioning method. As an intermediate format Petri net allows one to analyze properties of the specification and formally compute performance indices which are used in the partitioning process. This paper highlights methods of computing load balance, precedence relation degree and communication cost of behavioral description in order to perform the initial allocation along with partitioning. This paper is devoted to describing the initial allocation algorithm, although an overview of the general partitioning method is also presented.

关键词： hardware software performance Costs software algorithms Petri nets Performance analysis Partitioning algorithms software tools Clustering algorithms Communication system software

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HLS-based fast design space exploration of ad hoc hardware accelerators: A key tool for MPSoC synthesis on FPGA

HLS-based fast design space exploration of ad hoc hardware a...

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conference on Design and Architectures for Signal and Image Processing

作者： Youenn Corre Van-Trinh Hoang Jean-Philippe Diguet Dominique Heller Loïc Lagadec Laboratory-STICC Université de Bretagne Sud Lorient France Laboratory-STICC Université de Bretagne Occidentale Brest France

Over the last decade many academic and industrial system synthesis and codesign tools have been proposed to designers. However most of these tools are based on IP Libraries but either these libraries are incomplete or are simply not adapted to the targets and constraints. It means that something important is missing when it comes to real implementations. We address this question in this paper and propose a flexible, fast and practical solution. We use high level synthesis (HLS) to obtain fast estimations of hardware accelerators that can then be embedded within the loop of a larger design space exploration flow. Once some solutions are selected they can be directly reuse to synthesise and produce real IPs. In this paper we present the approach and the tool as a key component of our heterogeneous multiprocessor synthesis framework.

关键词： hardware Field programmable gate arrays Computer architecture Estimation Libraries IP networks software

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