Modern high-performance embedded systems face many challenges. systems must function in rapidly changing environments. Power/size constraints limit hardware size, while extreme performance requirements demand algorith...
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Modern high-performance embedded systems face many challenges. systems must function in rapidly changing environments. Power/size constraints limit hardware size, while extreme performance requirements demand algorithm specific architectures. hardware architectures must structurally adapt to achieve high performance with changing algorithms. Reconfigurable computing devices offer the promise of architectures that change in response to the changing environment. The primary difficulty in this approach lies in system design. A model-integrated approach is used in the design capture and synthesis of these systems. The target systems are built on a heterogeneous computing platform including configurable hardware, ASIC and general purpose processors and DSPs. This project is a DARPA Adaptive Computing systems funded effort, involving close cooperation with US ARMY/AMICOM.
The aim of this paper is to present the technology assessment of the N2C of CoWare inc. approach in the co-design/co-simulation problem. The test bench to be used is a telecommunication application implementing the Me...
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The aim of this paper is to present the technology assessment of the N2C of CoWare inc. approach in the co-design/co-simulation problem. The test bench to be used is a telecommunication application implementing the Medium Access (MAC) layer and the RF-IF part of the Physical (PHY) layer of the DECT protocol stack. These are part of a single-chip solution for the baseband processor of a mobile phone. This approach will be evaluated in comparison with the current industrial practice. N2C technology aims to fill very specific gaps in existing tool platforms and more specifically: high-level system modeling, HW-SW co-simulation and interface generation. It also supports additional co-design tasks like partitioning and co-synthesis. The final goal of this assessment is to isolate and point out the actual industrial needs for co-design through the evaluation of N2C according to the above characteristics.
Electronic control unit (ECU) manufacturers face the problem that, while most development processes now include simulation, rapid prototyping, and hardware-in-loop testing (HIL), the limitations of existing methods ar...
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Electronic control unit (ECU) manufacturers face the problem that, while most development processes now include simulation, rapid prototyping, and hardware-in-loop testing (HIL), the limitations of existing methods are preventing further growth. Perhaps the most bothersome limitation is the lack of an automated implementation tool which generates production code from the ECU model used during simulation and prototyping. Next on the wish list is a prototyping environment that accurately represents the actual target-constrained production system. This paper discusses these two problems and provides options for their solution.
The software designers at Hill Air Force Base have developed a voice recognition and speech synthesissystem (Voice Control) for use with the F-16 Analog Test Station Sustainment (FATSS) project. The Voice Control sys...
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The software designers at Hill Air Force Base have developed a voice recognition and speech synthesissystem (Voice Control) for use with the F-16 Analog Test Station Sustainment (FATSS) project. The Voice Control system is reliable, speaker independent, and has a total added hardware price tag of under $50.00 per station. In contrast to traditional voice recognition systems, operator training is not required. OO-ALC has developed a general-purpose internal interface (Voice Control) to the Speech Recognition and Text-To-Speech engines provided by Microsoft. Voice Control can be accessed by any 32-bit Windows software, which has windows messaging capability. This is available to standard programming languages such as LabWindows CVI, Borland or Microsoft C/C++, Visual Basic, or even commercial packages such as Lotus Notes, and Microsoft Word. Through Voice Control, the computer uses both video and voice prompts to request input from the operator. The operator is allowed to enter data and to control the software flow by voice command or from the keyboard or mouse. The Voice Control system allows for dynamic specification of a grammar set, or legal set of commands. The use of a reduced grammar set greatly increases recognition accuracy. The computer voice enables the operator to focus his attention away from the computer screen, which is required for activities such as probing a circuit card and taking readings. When the operator takes readings, the computer, to insure reliable entry, echoes his voice entries. With electronic tuning, speech synthesis allows the operator to hear the resulting reading, enabling him to focus on the circuit card instead of the constantly turning his head to see the computer screen. This paper describes the capability and functionality of the Voice Control system.
In this paper, rye propose the target board architecture of a rapid prototyping embedded system based on hardwaresoftwarecodesign. The target board contains a TMS320C30 DSP processor and up to four Xilinx XC4025E FP...
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ISBN:
(纸本)0818686235
In this paper, rye propose the target board architecture of a rapid prototyping embedded system based on hardwaresoftwarecodesign. The target board contains a TMS320C30 DSP processor and up to four Xilinx XC4025E FPGAs. Various communication channels between the C30 and the FPGAs are provided and a master-master computing paradigm is supported. HW/SW communication protocols, ranging from handshaking, batch to queue controlled, as well as the corresponding interfaces are described in VHDL and C codes respectively and can be easily augmented to the mapped design. A codesign implementation example based on G.728 LD-CELP speech decoder shows the proposed communication protocols and interfaces lead to very small rime and circuitry overhead.
The implementation of codesign applications generally requires the use of heterogeneous resources (e.g., processor cores, hard,rare accelerators) in one system. Interfacing hardware and software components together an...
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ISBN:
(纸本)0818684429
The implementation of codesign applications generally requires the use of heterogeneous resources (e.g., processor cores, hard,rare accelerators) in one system. Interfacing hardware and software components together and providing communications bent een them are particularly, error proned and time consuming tasks. Hence, on the basis of a generic architecture we propose an extended communication synthesis method that provides characterization of communications and their implementation scheme in the target architecture. This method takes place after partitioning and scheduling and can constitute the basis of a back end of a codesign framework leading to HW/SW integration.
This paper presents a codesign approach which incorporates communication protocol selection as a design parameter within hardware/software partitioning The presented approach takes into account data transfer rates dep...
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ISBN:
(纸本)0818686235
This paper presents a codesign approach which incorporates communication protocol selection as a design parameter within hardware/software partitioning The presented approach takes into account data transfer rates depending on communication protocol types and configurations and different operating frequencies of system components, i.e. CPUs, ASICs, and busses. It also takes into account the timing and area influences of drivers and driller calls needed to perform the communication. The approach is illustrated by a number of design space exploration experiments which use models of the PCI and USE communication protocols.
The proceedings contains 22 papers from Sixth international Workshop on hardware/softwarecodesign. Topics discussed include: system-level modeling;partitioning;communication and interface synthesis;co-simulation;sche...
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The proceedings contains 22 papers from Sixth international Workshop on hardware/softwarecodesign. Topics discussed include: system-level modeling;partitioning;communication and interface synthesis;co-simulation;scheduling;system on chip;system level modeling;distributed embedded systems;software timing analysis;instruction set simulator;abstract state machine models;instruction subsetting;and task-level memory hierarchy synthesis.
Rapid Prototyping has been proposed as a means to reduce development time and costs of real-rime systems. Our approach uses a heterogeneous, tightly coupled multiprocessor system based on off-the-shelf components as t...
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ISBN:
(纸本)0818684429
Rapid Prototyping has been proposed as a means to reduce development time and costs of real-rime systems. Our approach uses a heterogeneous, tightly coupled multiprocessor system based on off-the-shelf components as target architecture for an executable prototype, which is generated from the specification in an automated design process. Here, too, we aim to use existing tools and languages. But interface and communication synthesis, while being the key requirement of an automated translation of a abstract specification to a distributed system, is not yet state-of-the-art. The sensitivity of the overall performance of multiprocessor systems to overhead and latency introduced by communication on the other hand calls for an efficient interprocess communication (IPC). This paper presents concept and implementation of IPC functions which, implementing the message queue semantics of the specification language SDL, links the standard components of our multiprocessor system in an efficient manner, while at the same time providing the interface synthesis needed by the automated generation of a rapid prototype. The experiences gained when implementing a non-trivial, real-world CAN controller and monitor application on our rapid prototyping environment, are described as a first proof of concept.
In embedded systems, programmable peripherals are often coupled with the main programmable processor to achieve the desired functionality. Interfacing such peripherals with the processor qualifies as an important task...
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In embedded systems, programmable peripherals are often coupled with the main programmable processor to achieve the desired functionality. Interfacing such peripherals with the processor qualifies as an important task of hardwaresoftwarecodesign. In this paper, three important aspects of such interfacing, namely, the allocation of addresses to the devices, allocation of device drivers, and approaches to handle events and transitions have been discussed. The proposed approaches have been incorporated in a codesignsystem MICKEY. The paper includes a number of examples, taken from results synthesized by MICKEY, to illustrate the ideas.
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