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The design of a smart imaging core for automotive and consumer applications: a case study 05

The design of a smart imaging core for automotive and consum...

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proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Wido Kruijtzer Winfried Gehrke Victor Reyes Ghiath Alkadi Thomas Hinz Jorn Jöchalsky Bruno Steux Philips Research The Netherlands Philips Semiconductors Hamburg Germany University of Las Palmas GC Spain University of Hannover Germany École des Mines de Paris France

ISBN: (纸本)9781595931610

This paper describes the design of a low-cost, low-power smart imaging core that can be embedded in cameras. The core integrates an ARM 9 processor, a camera interface and two specific hardware blocks for image processing: a smart imaging coprocessor and an enhanced motion estimator. Both coprocessors have been designed using high-level synthesis tools taking the C programming language as a starting point. The resulting RTL code of each coprocessor has been synthesized and verified on an FPGA board. Two automotive and two mobile smart imaging applications are mapped onto the resulting smart imaging core. This mapping process of the original C++ applications onto the smart imaging core is also presented in this paper.

关键词： system level design image processing

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proceedings Design, Automation and Test in Europe conference and Exhibition

Proceedings Design, Automation and Test in Europe Conference...

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Design, Automation and Test in Europe conference and Exhibition

The following topics are dealt with: ambient intelligence - visions and achievements; energy-efficient memory systems; uncertainty; power-aware design and synthesis; test data compression; operating system abstraction and targeting; embedded software forum; analysis of jitter and noise for analogue systems; semiconductor device modelling and simulation; embedded system scheduling and analysis; DFT and BIST recent advances; analogue and RF modelling, simulation and optimisation; architectural level synthesis; scheduling in reconfigurable computing; delay testing and diagnosis; embedded operating systems for SoC; networks-on-chip; system level modelling; reconfigurable SoC; analogue and defect-oriented testing; energy aware software techniques; interconnect modelling and signal integrity; system level simulation; software optimisation; global approaches to layout synthesis; platform design and IP reuse methods; on-line testing and self-repair; safe automotive software development; mixed-signal design techniques; low power architectures; SoC testing; SAT based verification; highly integrated communication systems; chip estate zoning; asynchronous circuits; collaborative design and WWW-based tools; hardware/software codesign optimization; test pattern generation; low power software; application specific memory synthesis; CAD.

关键词： Intelligent networks Uncertain systems Data compression Operating systems Circuit noise Jitter Semiconductor device modeling Processor scheduling Design for testability Self-testing Circuit optimization High-level synthesis Reconfigurable architectures Mixed analog-digital integrated circuits Communication equipment Integrated circuit design Collaborative work Integrated circuit testing Asynchronous logic circuits Internet Semiconductor memories Design automation

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Java as a specification language for hardware-software systems

Java as a specification language for hardware-software syste...

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IEEE international conference on Computer-Aided Design

作者： Helaihel Olukotun Computer Systems Laboratory University of Stanford Stanford CA USA

The specification language is a critical component of the hardware-software co-design process since it is used for functional validation and as a starting point for hardware-software partitioning and co-synthesis. The paper proposes the Java programming language as a specification language for hardware-software systems. Java has several characteristics that make it suitable for system specification. However static control and data flow analysis of Java programs is problematic because Java classes are dynamically linked. The paper provides a general solution to the problem of statically analyzing Java programs using a technique that pre-allocates most class instances and aggressively resolves memory aliasing using global analysis. The output of the analysis is a control data flow graph for the input specification. The results for sample designs show that the analysis can extract fine to coarse-grained concurrency for subsequent hardware-software partitioning and co-synthesis steps of the hardware-software co-design process to exploit.

关键词： Specification languages

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Hw/Sw codesign of an ATM network interface card starting from a system level specification

Hw/Sw codesign of an ATM network interface card starting fro...

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URSI international Symposium on Signals, systems, and Electronics (ISSSE)

作者： N.-E. Zergainoh G.F. Marchioro A.A. Jerraya TIMA Laboratory-SLS Group Grenoble France

This paper discusses the uses of SDL for the co-design of an ATM network interface card (NIC). In this study, the initial specification is given in SDL. The architecture generation is made using Cosmos, a co-design tool for multiprocessor architecture. Several architectures are produced starting from the same initial SDL specification. The performance evaluation of these solutions was made using hardware/software co-simulation. This paper describes the experiment and the lessons learned about the capabilities and the restrictions of SDL and Cosmos for hardware/software co-design of distributed systems. The use of SDL allows for drastic reduction of the model size when compared to hardware/software model given in C/VHDL. SDL simulation may be 30 times faster than C/VHDL simulation.

关键词： Network interfaces hardware Design methodology Costs Productivity Protocols Laboratories Laser sintering Design automation Real time systems

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Interface co-synthesis techniques for embedded systems

Interface co-synthesis techniques for embedded systems

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IEEE international conference on Computer-Aided Design

作者： Pai Chou R.B. Ortega G. Borriello Department of Computer Science & Engineering University of Washington Seattle WA USA

A key aspect of the synthesis of embedded systems is the automatic integration of system components. This entails the derivation of both the hardware and software interfaces that will bind these elements together and permit them to communicate correctly and efficiently. Without the automatic synthesis of these interfaces, designers are not able to fully simulate and evaluate their systems. Frequently, they are discouraged from exploring the design space of different hardware/software partitions because practical concerns mandate minimizing changes late in the design cycle, thus leading to more costly implementations than necessary. This paper presents a set of techniques that form the basis of a comprehensive solution to the synthesis of hardware/software interfaces. software drivers and glue logic are generated to connect processors to peripheral devices, hardware co-processors, or communication interfaces while meeting bandwidth and performance requirements. We use as examples a set of devices that communicate over an infrared local communications network (highlighting a video wrist-watch display) to explain our techniques and the need for design space exploration tools for embedded systems.

关键词： Embedded system hardware Space exploration Network synthesis software performance Logic devices Coprocessors Bandwidth Optical fiber communication Communication networks

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Research on Intelligent Relic Interpretation system Based on a Large Language Model 24

Research on Intelligent Relic Interpretation System Based on...

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24th IEEE international conference on software Quality, Reliability and Security Companion, QRS-C 2024

作者： Guo, Jingjing Han, Xi Beijing Union University Beijing Key Laboratory of Information Service Engineering Beijing China College of Robotics Beijing Union University Beijing China

ISBN: (纸本)9798350365658

Nowadays, docents are the main force for inheriting and displaying human cultural heritage. However, the experience of visitors largely depends on their knowledge depth and updates. Large language models (LLMs) have demonstrated promising results across various fields due to their robust linguistic intelligence acquired through extensive data training. Nevertheless, training LLMs remains challenging due to their high hardware requirements. How can we integrate a LLM into a relic interpretation system without the need for extensive training? To this end, a solution is proposed by combining a LLM with a private domain database to create an intelligent relic interpretation system. This system encompasses the following functionalities:(1) Speech recognition and synthesis: Users input speech, and the system utilizes speech recognition technology to convert the speech into text. This text is then processed by the LLM, and the model's responses are synthesized into speech output;(2) Professional knowledge explanation: Leveraging a LLM and a private domain database to achieve more accurate and professional responses, compared to simply fine-tuning LLMs, this allows for the application of LLMs in vertical fields without the need for additional training;(3) Private domain database renewal: Two methods for updating the database are used: extracting relevant data from intranet sources and uploading data by professionals. The performance of the system is evaluated through comparison and ablation experiments. The results demonstrate that the system effectively addresses the limitations of traditional relic interpretation methods and introduces novel perspectives for relic interpretation. © 2024 IEEE.

关键词： Speech recognition

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ICENCO 2017 - 13th international Computer Engineering conference: Boundless Smart Societies

ICENCO 2017 - 13th International Computer Engineering Confer...

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13th international Computer Engineering conference, ICENCO 2017

ISBN: (纸本)9781538642665

The proceedings contain 71 papers. The topics discussed include: analysis of faults fixing system using rough sets: a case study in large-scale telecommunication company (telecom Egypt);a novel language-adaptable accent reduction software template;an economic model for cloud service composition based on user's preferences;learning the sit-to-stand human behavior: an inverse optimal control approach;performance analysis for diverse simulation scenarios for DSDV, DSR and AODV MANET routing protocols;providing QoS in contention management for software transactional memory;a data mining experimentation framework to improve Six Sigma projects;performance enhancement of free space optical (FSO) systems using polarized DWDM-OFDM technique under atmospheric disturbances;high-level synthesis hardware implementation and verification of HEVC DCT on SoC-FPGA;fuzzy logic-based clustering approach with mobile sink for WSNs;Twitter features distributions across similar labelers;energy aware ad-hoc on demand multipath distance vector (EAAOMDV);performance enhancement of free space optical (FSO) systems using polarized DWDM-OFDM technique under atmospheric disturbances;prediction of DNA methylation for every CpG loci in chromosome 18 in embryonic stem cells using support vector machine;and an energy efficient and adaptive clustering for wireless sensor network (CH-leach) using leach protocol.

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Architecture of a Search Engine for Massive Comparison in an Iris Biometric system

Architecture of a Search Engine for Massive Comparison in an...

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international Carnahan conference on Security Technology

作者： Judith Liu-Jimenez Raul Sanchez-Reillo Almudena Lindoso John G. Daugman Department Electronic Technology-Microelectronics Group Universidade Carlos III de Madrid Leganes Spain Spain Computer Laboratory University of Cambridge Cambridge UK

Biometrics is becoming one of the techniques most used for identification. Although these techniques are quite suitable for this purpose, when massive identification is required no for all of them there are dedicated devices. In this paper, the authors propose three different architectures for a search engine based on iris biometrics. These architectures relays on hardware-software codesign, reducing the expected time of comparison and the equipment cost

关键词： Search engines Biometrics Computer architecture Costs Security hardware Iris recognition Microelectronics Relays Identity management systems

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A chip-level security framework for assessing sensor data integrity: work-in-progress 18

A chip-level security framework for assessing sensor data in...

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proceedings of the international conference on hardware/software codesign and system synthesis

作者： Taimour Wehbe Vincent J. Mooney David C. Keezer Georgia Institute of Technology

ISBN: (纸本)9781538655627

The continuously increasing inter-connectivity of sensor nodes that form the basis of the Internet-of-Things results in new avenues of attack exploitable by adversaries to maliciously modify data captured by these nodes. In this work, we present a framework for detecting malicious hardware alterations that attempt to attack state-of-the-art microchips that form these sensor nodes. Specifically, we focus on extremely small hardware Trojans (HTs) that attempt to modify sensor data right away as the data is received on a state-of-the-art chip fabricated in an untrusted facility. We present a dual-chip approach composed of an untrusted state-of-the-art prover chip and a trusted verifier chip, where the verifier continuously challenges the prover at run-time to ensure correct operation and assess the integrity of the captured data. Our preliminary analysis of the proposed mechanism shows that HT attacks anywhere on the untrusted state-of-the-art chip are detected and flagged preventing maliciously altered data to be transmitted out of the sensor node.

关键词： embedded systems security hardware trojans malicious design modifications sensor networks data integrity security in hardware hardware attacks and countermeasures

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hardware-software codesign of resource-constrained real-time systems

Hardware-software codesign of resource-constrained real-time...

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IEEE international conference on Embedded and Real-Time Computing systems and Applications (RTCSA)

作者： Sungjoo Yoo Jinhwan Jeon Seongsoo Hong Kiyoung Choi Sch. of Electr. Eng. Seoul Nat. Univ. South Korea School of Electrical Engineering Seoul National University Seoul South Korea

This paper presents a hardware-software (HW-SW) partitioning algorithm to be used in HW-SW codesign of an embedded real-time system. The algorithm interacts with the period calibration method such that the period assignment and HW-SW partitioning of real-time tasks are considered in a single framework. The partitioning algorithm makes use of three heuristics and one random transformation rule in order to quickly find a feasible HW-SW partition which most likely leads to the minimum HW cost design. As an experimental study, two partitioning algorithms, one that is based on the proposed heuristics and the other based on simulated annealing have been implemented. We have performed preliminary experiments and present the result.

关键词： Real time systems Partitioning algorithms Timing Calibration Algorithm design and analysis Application specific integrated circuits Scheduling algorithm Kernel Costs Simulated annealing

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