The Canadian Microelectronics Corporation has developed and distributed a Rapid Prototyping Board (RPB) to facilitate research in hardware/software (HW/SW) codesign, case studies, applications and prototyping of proje...
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The Canadian Microelectronics Corporation has developed and distributed a Rapid Prototyping Board (RPB) to facilitate research in hardware/software (HW/SW) codesign, case studies, applications and prototyping of projects in embedded systems. This research develops a series of layers between hardware and software, exploiting the dynamically reconfigurable hardware of the RPB and creating the connection to host processes and software layers in general, both on the board itself, and between a HW/SW system downloaded to the board and its host workstation. In this paper we describe a new approach which uses object oriented technology as the basis for the system design methodology, the specifications and the implementation, providing a flexible and dynamic foundation, lending itself to further expansion and research in HW/SW codesign.
In this paper we study a collision detection algorithm and partition it into hardware and software parts to enhance the performance of the system and achieve the real time goal (25 frames/sec). We explore the design s...
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In this paper we study a collision detection algorithm and partition it into hardware and software parts to enhance the performance of the system and achieve the real time goal (25 frames/sec). We explore the design space to identify various feasible implementations on software, hardware, firmware and mixed platforms. The platforms considered are the Intel's processors and Sun ULTRA1 for software, MOTOROLA DSP56002 for firmware XILINX FPGAs for hardware. The mixed implementations include combinations of the above. A number of implementations discussed establish that factors such as time constraint, pin count and interface requirements strongly influence the design options.
The design of an embedded system is a process where the timing of the architecture should rake into account both the functionality and the timing performance while considering the heterogeneity of the hw and sw compon...
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ISBN:
(纸本)0818690992
The design of an embedded system is a process where the timing of the architecture should rake into account both the functionality and the timing performance while considering the heterogeneity of the hw and sw components. The goal of this paper is to present the new model developed during the SEED Esprit project, to estimate the software and hardware characteristics for cosimulation and profiling within the TOSCA codesign framework. The impact on the design space exploration of such an high-level cosimulation strategy has been tested by considering as a benchmark the reengineering of an industrial device.
This paper presents new results on an approach for solving satisfiability problems (SAT), i.e. creating a logic circuit that is specialized to solve each problem instance on Field Programmable Gate Array's (FPGAs)...
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ISBN:
(纸本)0818682558
This paper presents new results on an approach for solving satisfiability problems (SAT), i.e. creating a logic circuit that is specialized to solve each problem instance on Field Programmable Gate Array's (FPGAs). This approach becomes feasible due to the recent advances in FPGAs and high-level logic synthesis. In this approach, each SAT problem is automatically analyzed and implemented on FPCAs. We have developed an algorithm,which is suitable for implementing on a logic circuit. This algorithm is equivalent to the Davis-Putnam procedure with a powerful dynamic variable ordering heuristic. The algorithm does not have a large memory structure like a stack, thus sequential accesses to the memory do not become a bottleneck ill algorithm execution. Simulation results show that this method can solve a hard random 3-SAT problem with 400 variables within 20 minutes at a clock rate of 1MHz.
The aim of this paper is to present an arbiter synthesis approach stated as an arbitration scheme generation/selection problem. This approach may be easily inserted in an extendible systemcodesign methodology. It ass...
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hardware-software co-synthesis of an embedded system architecture entails partitioning of its specification into hardware and software modules suck that its real-time and other constraints are met. Embedded systems ar...
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hardware-software co-synthesis of an embedded system architecture entails partitioning of its specification into hardware and software modules suck that its real-time and other constraints are met. Embedded systems are generally specified in terms of a set of acyclic task graphs. For medium-to-large scale embedded systems, the task graphs are usually hierarchical in nature. The embedded system architecture, which is the output of the co-synthesissystem, may itself be non-hierarchical or hierarchical. Traditional non-hierarchical architectures create communication and processing bottlenecks, and are impractical for large embedded systems. Such systems require a large number of processing elements and communication links connected in a hierarchical manner, thus forming a hierarchical distributed architecture, to meet performance and cost objectives. In this paper, we address the problem of hardware-software co-synthesis of hierarchical distributed embedded system architectures from hierarchical or non-hierarchical task graphs. Our co-synthesis algorithm has the following features: 1) it supports periodic task graphs with real-time constraints, 2) it supports pipelining of task graphs, 3) it supports a heterogeneous set of PEs and communication links, 4) it allows both sequential and concurrent modes of communication and computation, 5) it employs a combination of preemptive and non-preemptive static scheduling, 6) it employs a new task clustering technique suitable for hierarchical task graphs, and 7) it uses the concept of association arrays to tackle the problem of multi-rate tasks encountered in multimedia systems. We show how our co-synthesis algorithm can be easily extended to consider fault tolerance or low power objectives or both. Although hierarchical architectures have been proposed before, to the best of our knowledge, this is the first time the notion of hierarchical task graphs and hierarchical architectures has been supported in a co-synthesis algorithm
This article describes a new approach to synthesise dedicated hardware from a system specification using the Java language. The new compiler named GALADRIELstarts from Java classfiles produced from the initial Java sp...
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The implementation of codesign applications generally requires the use of heterogeneous resources (e.g., processor cores, hardware accelerators) in one system. Interfacing hardware and software components together and...
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The implementation of codesign applications generally requires the use of heterogeneous resources (e.g., processor cores, hardware accelerators) in one system. Interfacing hardware and software components together and providing communications between them are particularly error prone and time consuming tasks. Hence, on the basis of a generic architecture we propose an extended communication synthesis method that provides characterization of communications and their implementation scheme in the target architecture. This method takes place after partitioning and scheduling and can constitute the basis of a back end of a codesign framework leading to HW/SW integration.
In embedded systems, programmable peripherals are often coupled with the main programmable processor to achieve the desired functionality. Interfacing such peripherals with the processor qualifies as an important task...
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In embedded systems, programmable peripherals are often coupled with the main programmable processor to achieve the desired functionality. Interfacing such peripherals with the processor qualifies as an important task of hardwaresoftwarecodesign. In this paper, three important aspects of such interfacing, namely, the allocation of addresses to the devices, allocation of device drivers, and approaches to handle events and transitions have been discussed. The proposed approaches have been incorporated in a codesignsystem MICKEY. The paper includes a number of examples, taken from results synthesized by MICKEY, to illustrate the ideas.
Electronic systems need to accommodate rapidly changing product specifications and to reduce design costs together with design turn-around time. To be able to re-use part of previous designs and to be able to include ...
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ISBN:
(纸本)0818683503
Electronic systems need to accommodate rapidly changing product specifications and to reduce design costs together with design turn-around time. To be able to re-use part of previous designs and to be able to include new functionality rapidly, system designers tend to use micro-controllers and Digital Signal Processors (DSPs) as much as possible. For performance reasons may be forced to design special purpose hardware, but even then there is a strong motivation toward the re-use of parts already designed. This trend will change the industrial landscape and will make the trade and assembly of Intellectual Properties (IPs) embodied in layouts, RTL designs, and software programs indispensable. We believe that system design should be based on the use of one or more formal models to describe the behavior of the system at a high level of abstraction, before a decision on its decomposition into hardware and software components is taken. Design should then be based on a sequence consisting of the initial functional design (i.e., specifying what the system is intended to do) and its analysis, the mapping of such functional description into an architecture, and the consequent performance evaluation. The final implementation of the system should be made using automatic synthesis as much as possible from this high level of abstraction, to ensure implementations that are "correct by construction." Validation (through simulation or verification) should be done at the highest possible levels of abstraction.
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