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3rd IEEE international conference on Information Technology, Big Data and Artificial Intelligence, ICIBA 2023

作者： Gong, Jing Zheng, Shiji Liang, Jialiang Dong, Yan Qiu, Bijin Song, Wei Jiangmen Polytechnic College of Information Engineering Jiangmen China

ISBN: (纸本)9781665490788

Most of the current aerial images of UAVs are stitched together with the help of image post-processing software on the PC side, which has certain inconvenience. Based on the Android platform, the aerial images are transmitted back to the cell phone, and OpenCV is used to realize the fast-stitching and synthesis of the aerial images of UAVs. At the same time, considering the limitation of hardware image processing capability of mobile devices, the method is optimized and experimentally verified, and the results show that the image stitching effect on the mobile side meets the expectation. © 2023 IEEE.

关键词： Android (operating system)

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Rapid prototyping of dataflow programs on hardware/software architectures

Rapid prototyping of dataflow programs on hardware/software ...

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Annual Hawaii international conference on system Sciences (HICSS)

作者： M. Eisenring J. Teich L. Thiele Computer Engineering and Communication Networks Lab (TIK) Swiss Federal Institute of Technology Zurich Switzerland

In this paper, the problem of automatically mapping large-grain dataflow programs onto heterogeneous hardware/software architectures is treated. Starting with a given hardware/software partition, interfaces are inserted into the specification to account for communication, in particular across hardware/software boundaries. Depending on the target architecture, the interfaces are refined according to given communication constraints (bus protocols, memory mapping, interrupts, DMA, etc.). A framework is described that uses an object-oriented approach to transform a given dataflow graph and to generate code for the actors as well as for the interfaces. The object-orientation enables an easy migration (retargeting) of typical communication primitives to other target architectures.

关键词： hardware Computer architecture Control system synthesis Object oriented modeling Buffer storage Computer networks Data engineering Communication networks Protocols Automatic control

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software synthesis for complex reactive embedded systems

Software synthesis for complex reactive embedded systems

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： F. Balarin M. Chiodo Cadence Berkeley Laboratories USA Cadence Design Systems Inc. USA

We propose a software synthesis procedure for reactive embedded system. The procedure is an extension of the approach in the POLIS co-design framework. In our approach, control parts of the system are represented in a decomposed form, enabling more complex control structures to be represented. We propose a synthesis procedure for this representation that avoids unnecessary evaluations of the data part, as well as the overhead of run-time scheduling.

关键词： Embedded software Embedded system hardware software performance software standards Network synthesis Communication system control Data structures Microwave ovens Watches

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Efficient Decentralized LTL Monitoring Framework Using Tableau Technique

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 87-87页

作者： Bataineh, Omar Rosenblum, David S. Reynolds, Mark Natl Univ Singapore Sch Comp 13 Comp Dr Singapore 117417 Singapore Univ Western Australia Comp Sci & Software Engn 35 Stirling Hwy Crawley WA 6009 Australia

This paper presents a novel framework for decentralized monitoring of Linear Temporal Logic (LTL) formulas, under the situation where processes are synchronous and the formula is represented as a tableau. The tableau technique allows one to construct a semantic tree for the input LTL formula, which can be used to optimize the decentralized monitoring of LTL in various ways. Given a system P and an LTL formula phi, we construct a tableau T-phi. The tableau T-phi is used for two purposes: (a) to synthesize an efficient round-robin communication policy for processes, and (b) to find the minimal ways to decompose the formula and communicate observations of processes in an efficient way. In our framework, processes can propagate truth values of both atomic and compound formulas (non-atomic formulas) depending on the syntactic structure of the input LTL formula and the observation power of processes. We demonstrate that this approach of decentralized monitoring based on tableau construction is more straightforward, more flexible, and more likely to yield efficient solutions than alternative approaches.

关键词： Decentralized monitoring Linear Temporal Logic (LTL) tableau

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Coherent Extension, Composition, and Merging Operators in Contract Models for system Design

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 86-86页

作者： Passerone, Roberto Romeo, Inigo Incer Sangiovanni-Vincentelli, Alberto L. Univ Trento Dipartimento Ingn & Sci Informaz Via Sommar 9 I-38123 Trento Italy Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

Contract models have been proposed to promote and facilitate reuse and distributed development. In this paper, we cast contract models into a coherent formalism used to derive general results about the properties of their operators. We study several extensions of the basic model, including the distinction between weak and strong assumptions and maximality of the specification. We then analyze the disjunction and conjunction operators, and show how they can be broken up into a sequence of simpler operations. This leads to the definition of a new contract viewpoint merging operator, which better captures the design intent in contrast to the more traditional conjunction. The adjoint operation, which we call separation, can be used to repartition the specification into different viewpoints. We show the symmetries of these operations with respect to composition and quotient.

关键词： Interface contract merging conformance separation

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proceedings. Third ACM & IEEE international conference on Formal Methods and Models for Co-Design (IEEE Cat. No. 05EX1093)

Proceedings. Third ACM & IEEE International Conference on Fo...

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ACM and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

The following topics are dealt with: hardware synthesis; hardware languages; hardware semantics; software verification; system-level verification; model checking; microarchitectural specification; microarchitectural v...

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Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems 1994年 96-100页

作者： Henkel, Joerg Ernst, Rolf Holtmann, Ullrich Benner, Thomas Technische Universitaet Braunschweig Braunschweig Germany

Previously, we had presented the system COSYMA for hardware/software co-synthesis of small embedded controllers [ErHeBe93]. Target system of COSYMA is a core processor with application specific co-processors. The system speedup for standard programs compared to a single 33MHz RISC processor solution with fast, single cycle access RAM was typically less than 2 due to restrictions in high-level co-processor synthesis, and incorrectly estimated back end tool performance, such as hardware synthesis, compiler optimization and communication optimization. Meanwhile, a high-level synthesis tool for high-performance co-processors in co-synthesis has been developed. This paper explains the requirements and the main features of the high-level synthesis system and its integration into COSYMA. The results show a speedup of 10 in most cases. Compared to the speedup, the co-processor size is very small.

关键词： Logic design

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A low-cost and low-power multi-standard video encoder 03

A low-cost and low-power multi-standard video encoder

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proceedings of the 1st IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： R. Peset Llopis R. Sethuraman C. Alba Pinto H. Peters S. Maul M. Oosterhuis Philips Research Laboratories Eindhoven The Netherlands

ISBN: (纸本)9781581137422

Video encoders are an important IP block in mobile multimedia systems. In this paper, we describe a low-cost low-power multi-standard (MPEG4, JPEG, and H.263) video/image encoder. The low-cost and low-power aspects are achieved by the right choice of algorithms and architectures. In the algorithm front, an embedded compression technique for reducing the size of loop memory has enabled a single-chip low-cost realization of the encoder. In the architectural front, an efficient hardware-software partitioning has contributed to the design of a low-power encoder. Further, the hardware components that accelerate the kernels of encoding are implemented as application specific instruction-set processors (ASIPs) thereby providing flexibility to address multi-standard encoding. The power and area estimates for the encoder for [email protected] in 0.18um CMOS technology are 30mW and 20mm2 respectively including the loop memory.

关键词： multi-standard low-cost hardware/software partitioning low-power video encoder ASIPs

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CRAMES: compressed RAM for embedded systems 05

CRAMES: compressed RAM for embedded systems

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proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Lei Yang Robert P. Dick Haris Lekatsas Srimat Chakradhar Northwestern University Evanston IL NEC Laboratories America Princeton NJ

ISBN: (纸本)9781595931610

Memory is a scarce resource in many embedded systems. Increasing memory often increases packaging and cooling costs, size, and energy consumption. This paper presents CRAMES, an efficient software-based RAM compression technique for embedded systems. The goal of CRAMES is to dramatically increase effective memory capacity without hardware design changes, while maintaining high performance and low energy consumption. To achieve this goal, CRAMES takes advantage of an operating system's virtual memory infrastructure by storing swapped-out pages in compressed format. It dynamically adjusts the size of the compressed RAM area, protecting applications capable of running without it from performance or energy consumption penalties. In addition to compressing working data sets, CRAMES also enables efficient in-RAM filesystem compression, thereby further increasing RAM capacity. CRAMES was implemented as a loadable module for the Linux kernel and evaluated on a battery-powered embedded system. Experimental results indicate that CRAMES is capable of doubling the amount of RAM available to applications. Execution time and energy consumption for a broad range of examples increase only slightly, by averages of 0.35% and 4.79%. In addition, this work identifies the software-based compression algorithms that are most appropriate for low-power embedded systems.

关键词： memory embedded system compression

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A systemC-based modular design and verification framework for C-model reuse in a HW/SW-codesign design flow

A systemC-based modular design and verification framework fo...

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international conference on Distributed Computing systems Workshop

作者： O. Blaurock Department of Computer Science University of Hamburg Germany

Rising the level of abstraction in system modelling allows early verification of the system functionality, reducing the risk of long redesign cycles. Moving to a new flow introducing systemC as SDL allows the reuse of existing high-level C-models. A framework is presented that allows C-model integration and the connection of modules located at different levels of abstraction without the need to implement the communication or introduce adaptors to translate between the abstraction levels. The focus of the approach lies on high acceptance by the designers coming from a C and HDL based top-down design methodology.

关键词： Design methodology software systems Process design Concurrent computing Electrical equipment industry Industrial control Computer science hardware design languages Time to market Embedded software

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