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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1553 条记录，以下是1321-1330 订阅

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CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems

CORDS: Hardware-software co-synthesis of reconfigurable real...

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proceedings of the 1998 IEEE/ACM international conference on Computer-Aided Design, ICCAD

作者： Dick, Robert P. Jha, Niraj K. Princeton Univ Princeton United States

Field programmable gate arrays (FPGAs) are commonly used in embedded systems. Although it is possible to reconfigure some FPGAs while an embedded system is operational, this feature is seldom exploited. Recent improvements in the flexibility and reconfiguration speed of FPGAs have made it practical to reconfigure them dynamically, reducing the amount of hardware required in an embedded system. We have developed a system, called CORDS, which synthesizes multi-rate, real-time, periodic distributed embedded systems containing dynamically reconfigurable FPGAs. Executing different tasks on the same FPGA requires that potentially time-consuming reconfiguration be carried out between tasks. CORDS uses a novel preemptive, dynamic priority, multi-rate scheduling algorithm to deal with this problem. To the best of our knowledge, dynamically reconfigured FPGAs have not previously been used in hardware-software co-synthesis of embedded systems. Experimental results indicate that using dynamically reconfigured FPGAs in distributed real-time embedded systems has the potential to reduce their price and allow the synthesis of architectures which meet system specifications that would otherwise be infeasible.

关键词： Embedded systems

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Implementing C designs in hardware: A full-featured ANSI C to RTL Verilog compiler in action

Implementing C designs in hardware: A full-featured ANSI C t...

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1998 international Verilog HDL conference and VHDL international Users Forum

作者： Soderman, D Panchul, Y CompiLog Corp San Jose CA 95125 USA

ISBN: (纸本)0818684151

The usage of a new full-featured ANSI C to synthesizable RTL Verilog compiler for implementing system-level algorithms in hardware is described. The compiler automatically creates multiple Verilog state machines for loops, on-chip register and arithmetic macros, and external memory interfaces. A two-pass compile interfacing with a synthesis tool allows insertion of registers and wait states to balance propagation delays for maximum performance. This design methodology is demonstrated using several compression-decompression, prime number, and sorting algorithms. Compiled RTL Verilog designs have been synthesized into FPGAs and ASICs. The compression-decompression algorithm executes in nearly one quarter the clock cycles using hardware versus software on a PentiumPro. This cycle efficiency is due to variable storage in simple registers, clock packing techniques, and functional level parallelism. Efficient clock packing is demonstrated with a prime number generator algorithm which executes in 25x fewer clock cycles compared to Pentium software execution.

关键词： Program compilers

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proceedings of the 1998 31st Annual Hawaii international conference on system Sciences. Part 7 (of 7)

Proceedings of the 1998 31st Annual Hawaii International Con...

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The 1998 31st Annual Hawaii international conference on system Sciences, HICSS-31

The proceedings contains 92 papers from the Thirty-First Annual Hawaii international conference on software Technology Track. Topics discussed include: managing large scale computational markets;mobile intelligent agents;integrating Java-based mobile agents;Internet protocol (IP) multicast models;adaptive routing;loops run-time parallelization;parallel tasks mapping;software controlled cache prefetching;overlapping programs;generic steering and visualization middleware;transaction-based computational steering;tuning parallel programs;logic synthesis and reconfigurable hardware;dataflow programs rapid prototyping;object-oriented layered approach;embedded systems;case base retrieval;and logic programming.

关键词： Computer aided software engineering

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Interface synthesis: A vertical slice from digital logic to software components

Interface synthesis: A vertical slice from digital logic to ...

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proceedings of the 1998 IEEE/ACM international conference on Computer-Aided Design, ICCAD

作者： Borriello, Gaetano Lavagno, Luciano Ortega, Ross B. Univ of Washington Seattle WA United States

Interface synthesis seeks to automate the process of interconnecting components. There are many levels of interconnection that must be considered including electrical, power, logic, register-transfer, device drivers, and higher software levels. This presentation will cover a vertical slice of the interfacing problem from digital logic up to coordinating communications between software components. The focus will be within an embedded systems context where the interfacing is between processors and memory and peripheral blocks as is the case in system-on-a-chip design. The structure of the tutorial will parallel the history of CAD efforts in this area. We will begin with the early work in interface specification and logic synthesis then proceed on to the problems of interconnecting hardware to processors and their software, and finish with purely software interfaces involving inter-process communication and protocols between multiple processors. At each level we will discuss specification, synthesis, and verification aspects as well as highlight the currently available tools and on-going research efforts.

关键词： Interfaces (computer)

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An object-oriented layered approach to interfaces for hardware/software codesign of embedded systems

An object-oriented layered approach to interfaces for hardwa...

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Annual Hawaii international conference on system Sciences (HICSS)

作者： W.B. Gardner M. Serra VLSI Design & Test Group Department of Computer Science University of Victoria Victoria BC Canada

The Canadian Microelectronics Corporation has developed and distributed a rapid prototyping board (RPB) to facilitate research in hardware/software (HW/SW) codesign, case studies, applications and prototyping of projects in embedded systems. This research develops a series of layers between hardware and software, exploiting the dynamically reconfigurable hardware of the RPB and creating the connection to host processes and software layers in general, both on the board itself, and between a HW/SW system downloaded to the board and its host workstation. We describe a new approach which uses object oriented technology as the basis for the system design methodology, the specifications and the implementation, providing a flexible and dynamic foundation, lending itself to further expansion and research in HW/SW codesign.

关键词： hardware Embedded software Embedded system Field programmable gate arrays Microelectronics Application software Connectors system testing software prototyping Educational institutions

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Communication and interface synthesis on a rapid prototyping hardware/software codesign system

Communication and interface synthesis on a rapid prototyping...

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international Symposium on system synthesis

作者： Yin-Tsung Hwang Yuan-Hung Wang Department of Electronic Engineering National Yunlin University of Science and Technology Yunlin Taiwan

ISBN: (纸本)0818686235

In this paper, we propose the target board architecture of a rapid prototyping embedded system based on hardware software codesign. The target board contains a TMS320C30 DSP processor and up to four Xilinx XC4025E FPGAs. Various communication channels between the C30 and the FPGAs are provided and a master-master computing paradigm is supported HW/SW communication protocols, ranging from handshaking, batch to queue controlled, as well as the corresponding interfaces are described in VHDL and C codes respectively and can be easily augmented to the mapped design. A codesign implementation example based on G.728 LD-CELP speech decoder shows the proposed communication protocols and interfaces lead to very small time and circuitry overhead.

关键词： Prototypes software prototyping Field programmable gate arrays Protocols Computer architecture Embedded system hardware Embedded software Digital signal processing Communication channels

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Integrating communication protocol selection with partitioning in hardware/software codesign

Integrating communication protocol selection with partitioni...

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international Symposium on system synthesis

作者： P.V. Knudsen J. Madsen Department of Information Technology Technical University of Denmark Denmark

This paper presents a codesign approach which incorporates communication protocol selection as a design parameter within hardware/software partitioning. The presented approach takes into account data transfer rates depending on communication protocol types and configurations, and different operating frequencies of system components, i.e. CPUs, ASICs, and busses. It also takes into account the timing and area influences of drivers and driver calls needed to perform the communication. The approach is illustrated by a number of design space exploration experiments which use models of the PCI and USB communication protocols.

关键词： Protocols hardware Universal Serial Bus Frequency Coprocessors Information technology Timing Space exploration Libraries Communication channels

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An image processing system developed under the codesign approach of COMITY

An image processing system developed under the codesign appr...

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URSI international Symposium on Signals, systems, and Electronics (ISSSE)

作者： C. Adida X. Granger P. Lamaty M. Boubal Electronics & Software Departments Business Unit Equipment-AEROSPATIALE Missiles Bourges France

We present the Aerospatiale experiment developed under the co-design approach of COMITY (codesign Method and integrated Tools for advanced embedded systems). Different critical tasks of the mixed hardware-software design are examined. Notably, the high level description and simulation with SDL language are discussed, and also the progress on the MUSIC tool (a codesign tool developed at TIMA laboratory).

关键词： Image processing hardware Multiple signal classification Design engineering software prototyping Consumer electronics Embedded software software tools Missiles Embedded system

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An analysis-based approach to composition of distributed embedded systems

An analysis-based approach to composition of distributed emb...

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international Workshop on hardware/software codesign (CODES)

作者： P. Chou G. Borriello Department of Computer Science and Engineering University of Washington Seattle WA USA

The growing complexity in the functionality and system architecture of embedded systems has motivated designers to raise the level of abstraction by composing the system with a mix of reusable and system-specific components. Currently, these components assume specific programming models that make them difficult to compose or retarget. The modal process model addresses the problem of control composition by separating the synchronization semantics from state unification, and by supporting automatic synthesis of control communication onto distributed architectures. By avoiding over-specifying the behavior, the components can be made more composable and the designer can more easily choose the least expensive synchronization semantics for implementing the composition. To help designers evaluate their choice, we propose a method for analyzing the properties of the composed system, including the detection of potential deadlock and livelock situations.

关键词： Embedded system Communication system control Control system synthesis system recovery Computer science Design engineering Automatic control Message passing Distributed control Process design

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Communication synthesis for distributed embedded systems 98

Communication synthesis for distributed embedded systems

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proceedings of the 1998 IEEE/ACM international conference on Computer-Aided Design, ICCAD

作者： Ortega, Ross B. Borriello, Gaetano Univ of Washington Bothell WA United States

ISBN: (纸本)9781581130089

Designers of distributed embedded systems face many challenges in determining the tradeoffs when defining a system architecture or retargeting an existing design. Communication synthesis, the automatic generation of the necessary software and hardware for system components to exchange data, is required to more effectively explore the design space and automate very error-prone tasks. This paper examines the problem of mapping a high-level specification to an arbitrary architecture that uses specific, common bus protocols for inter-processor communication. The communication model presented allows for easy retargeting to different bus topologies, protocols, and illustrates that global considerations are required to achieve a correct implementation. An algorithm is presented that partitions multihop communication timing constraints to effectively utilize the bus bandwidth along a message path. The communication synthesis tool is integrated with a system co-simulator to provide performance data for a given mapping.

关键词： Computer aided network analysis

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