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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1552 条记录，以下是1341-1350 订阅

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Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design) 09

Using GPCE principles for hardware systems and accelerators:...

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proceedings of the eighth international conference on Generative programming and component engineering

作者： Rishiyur S. Nikhil Bluespec Inc. Waltham MA USA

ISBN: (纸本)9781605584942

Moore's Law has precipitated a crisis in the creation of hardware systems (ASICs and FPGAs)-how to design such enormously complex concurrent systems quickly, reliably and affordably? At the same time, portable devices, the energy crisis, and high performance computing present a related challenge-how to move complex and high-performance algorithms from software into hardware (for more speed and/or energy efficiency)?In this talk I will start with a brief technical introduction to BSV, a language that directly addresses these concerns. It uses ideas from Guarded Atomic Actions (cf. Term Rewriting systems, TLA+, Unity, and EventB) to address complex concurrency with scalability. It borrows from Haskell (types, type classes, higher-order functions) for robustness and powerful program generation (a.k.a. "static elaboration" to HW designers). And it is fully synthesizable (compilable) into high-quality RTL (Verilog/VHDL). I will then describe some of the remarkable projects that BSV has enabled in industry and academia today.

关键词： energy efficient computing high performance computing hybrid computing fpga term rewriting systems bluespec systemverilog hardware accelerators bsv hardware/software codesign high level synthesis haskell

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Towards a multi-formalism framework for architectural synthesis: the ASAR project 94

Towards a multi-formalism framework for architectural synthe...

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proceedings of the 3rd international workshop on hardware/software co-design

作者： M. Auguin M. Belhadj J. benzakki C. Carrière G. Durrieu Th. Gautier M. Israël P. Le Guernic M. Lemaître E. Martin P. Quinton L. Rideau F. Rousseau O. Sentieys I3S IRISA LIVE CERT-Onera IRISA-INRIA LISTI IRISA-CNRS INRIA-Sophia LASTI

This paper describes a research project - named ASAR - grouping together six french research teams, oriented towards architectural and system synthesis. A main concern of this project is hardware/software codesign and...

ISBN: (纸本)9780818663154

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ReSQM: Accelerating Database Operations Using ReRAM-Based Content Addressable Memory

ReSQM: Accelerating Database Operations Using ReRAM-Based Co...

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作者： Li, Huize Jin, Hai Zheng, Long Liao, Xiaofei National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

The huge amount of data enforces great pressure on the processing efficiency of database systems. By leveraging the in-situ computing ability of emerging nonvolatile memory, processing-in-memory (PIM) technology shows great potential in accelerating database operations against traditional architectures without data movement overheads. In this article, we introduce ReSQM, a novel ReCAM-based accelerator, which can dramatically reduce the response time of database systems. The key novelty of ReSQM is that some commonly used database queries that would be otherwise processed inefficiently in previous studies can be in-situ accomplished with massively high parallelism by exploiting the PIM-enabled ReCAM array. ReSQM supports some typical database queries (such as SELECTION, SORT, and JOIN) effectively based on the limited computational mode of the ReCAM array. ReSQM is also equipped with a series of hardware-algorithm co-designs to maximize efficiency. We present a new data mapping mechanism that allows enjoying in-situ in-memory computations for SELECTION operating upon intermediate results. We also develop a count-based ReCAM-specific algorithm to enable the in-memory sorting without any row swapping. The relational comparisons are integrated for accelerating inequality join by making a few modifications to the ReCAM cells with negligible hardware overhead. The experimental results show that ReSQM can improve the (energy) efficiency by $611\times $ ( $193\times $ ), $19\times $ ( $17\times $ ), $59\times $ ( $43\times $ ), and $307\times $ ( $181\times $ ) in comparison to a 10-core Intel Xeon E5-2630v4 processor for SELECTION, SORT, equi-join, and inequality join, respectively. In contrast to state-of-the-art CMOS-based CAM, GPU, FPGA, NDP, and PIM solutions, ReSQM can also offer $2.2\times 39\times $ speedups. © 1982-2012 IEEE.

关键词： Query languages

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Accelerating full-system simulation and app analysis through focused multi-granularity profiling

Accelerating full-system simulation and app analysis through...

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Electronic system Level synthesis conference (ESLsyn)

作者： Tzu-Hsiang Su Wei-Shan Wu Chen-Te Chou Yuan-Chun Cheng Meng-Ting Tsai Tien-Fu Chen Dept. of CS National Chiao Tung University Taiwan R.O.C. Macronix International Co. Ltd.

Faced with the rapid divergence of hardware used on embedded devices, there is a need for a tool that can efficiently assist with hardware/software co-design and architecture verification. Speeding up those ESL phases greatly reduces the length of development periods. To address this issue, our work implements a novel multi-granularity tracer for Android's simulator to provide ESL hardware design performance analysis and verification. In addition, we propose a flexible ESL module interface for system hardware designers to explore new hardware components via simple modules. Our work also enables software developers to identify performance bottleneck and assess software performance of new hardware components. Our case studies and experimental results show that our multi-granularity Android tracer can strip away irrelevant information to shave time off the architecture development period.

关键词： Instruments hardware Androids Humanoid robots Generators Virtual machining Smart phones

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Interface synthesis in heterogeneous system-level DSP design tools

Interface synthesis in heterogeneous system-level DSP design...

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international conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： J.L. Pino M.C. Williamson E.A. Lee Department of Electrical Engineering and Computer Science University of California Berkeley CA USA

We describe a framework that constructs interfaces between simulation tools and real-time prototyping hardware in a high-level DSP synthesis environment. A goal of this work is to abstract the concept of the interface so that customized links are not required between each simulation and hardware engine. To support a new engine, the DSP system designer must define two pairs of communication primitives between the new tool and host workstation. The interface construction mechanism provides incremental compilation of subsystems in a system specification into the high-level DSP synthesis environment. We illustrate this framework with practical examples that have been constructed in Ptolemy.

关键词： Digital signal processing Engines hardware Computational modeling Virtual prototyping Workstations Discrete event simulation Limiting Computer simulation software prototyping

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11th international conference on Field-Programmable Logic andApplications 2001

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11th international conference on Field-Programmable Logic and Applications, FPL 2001

ISBN: (纸本)3540424997

The proceedings contain 74 papers. The special focus in this conference is on Invited Keynote 1 and Architectural Frameworks. The topics include: Technology trends and adaptive computing;prototyping framework for reconfigurable processors;an emulator for exploring RaPiD configurable computing architectures;a new placement method for direct mapping into LUT-based FPGAs;fGREP - fast generic routing demand estimation for placed FPGA circuits;macrocell architectures for product term embedded memory arrays;gigahertz reconfigurable computing using SiGe HBT BiCMOS FPGAs;memory synthesis for FPGA-based reconfigurable computers;implementing a hidden markov model speech recognition system in programmable logic;implementation of (normalised ) RLS lattice on virtex;accelerating matrix product on reconfigurable hardware for signal processing;static profile-driven compilation for FPGAs;synthesizing RTL hardware from java byte codes;from behavioral specification to multi-FPGA-prototype;secure configuration of field programmable gate arrays;single-chip FPGA implementation of the advanced encryption standard algorithm;jbits™ implementations of the advanced encryption standard (rijndael );task-parallel programming of reconfigurable systems;chip-based reconfigurable task management;configuration caching and swapping;multiple stereo matching using an extended architecture;implementation of a NURBS to bézier conversor with constant latency;reconfigurable frame-grabber for real-time automated visual inspection (RT-AVI ) systems;processing models for the next generation network;tightly integrated placement and routing for FPGAs;a tool for the simultaneous placement and detailed routing of gate-arrays;reconfigurable router modules using network protocol wrappers;development of a design framework for platform-independent networked reconfiguration of software and hardware and the molen ρμ-coded processor.

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Bluespec system Verilog: efficient, correct RTL from high level specifications

Bluespec System Verilog: efficient, correct RTL from high le...

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ACM and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： R. Nikhil Bluespec Inc. Waltham MA USA

Bluespec system Verilog is an EDL toolset for ASIC and FPGA design offering significantly higher productivity via a radically different approach to high-level synthesis. Many other attempts at high-level synthesis have tried to move the design language towards a more software-like specification of the behavior of the intended hardware. By means of code samples, demonstrations and measured results, we illustrate how Bluespec system Verilog, in an environment familiar to hardware designers, can significantly improve productivity without compromising generated hardware quality.

关键词： hardware Productivity High level synthesis Atomic measurements Application specific integrated circuits Field programmable gate arrays Flow graphs Scheduling Logic design Predictive models

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Global Winning Conditions in synthesis of Distributed systems with Causal Memory 30

Global Winning Conditions in Synthesis of Distributed System...

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30th EACSL Annual conference on Computer Science Logic, CSL 2022

作者： Finkbeiner, Bernd Gieseking, Manuel Hecking-Harbusch, Jesko Olderog, Ernst-Rüdiger CISPA Helmholtz Center for Information Security Saarbrücken Germany University of Oldenburg Germany

ISBN: (纸本)9783959772181

In the synthesis of distributed systems, we automate the development of distributed programs and hardware by automatically deriving correct implementations from formal specifications. For synchronous distributed systems, the synthesis problem is well known to be undecidable. For asynchronous systems, the boundary between decidable and undecidable synthesis problems is a long-standing open question. We study the problem in the setting of Petri games, a framework for distributed systems where asynchronous processes are equipped with causal memory. Petri games extend Petri nets with a distinction between system places and environment places. The components of a distributed system are the players of the game, represented as tokens that exchange information during each synchronization. Previous decidability results for this model are limited to local winning conditions, i.e., conditions that only refer to individual components. In this paper, we consider global winning conditions such as mutual exclusion, i.e., conditions that refer to the state of all components. We provide decidability and undecidability results for global winning conditions. First, we prove for winning conditions given as bad markings that it is decidable whether a winning strategy for the system players exists in Petri games with a bounded number of system players and one environment player. Second, we prove for winning conditions that refer to both good and bad markings that it is undecidable whether a winning strategy for the system players exists in Petri games with at least two system players and one environment player. Our results thus show that, on the one hand, it is indeed possible to use global safety specifications like mutual exclusion in the synthesis of distributed systems. However, on the other hand, adding global liveness specifications results in an undecidable synthesis problem for almost all Petri games. © Bernd Finkbeiner, Manuel Gieseking, Jesko Hecking-Harbusch, and Ernst-Rüdiger

关键词： Computability and decidability

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Object-oriented design of an expandable hardware description language analyzer for a high-level synthesis system

Object-oriented design of an expandable hardware description...

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Annual Hawaii international conference on system Sciences (HICSS)

作者： L. Yang M.A. Perkowski D. Smith ImageBuilder Software Portland OR USA Department of Electrical Engineering Portland State University Portland OR USA

The paper presents a new approach to high-level synthesis system design in which object-oriented programming techniques are used to construct an expansible hardware description language (HDL) analyzer. There are several major advantages of this new methodology over the traditional top-down approaches. The object-oriented data model for high-level synthesis systems is shown to be a better way to model the high-level synthesis design entities. A formal object oriented programming(OOP) model of high-level synthesis and systematic ways of expanding the system are also described. This design style influences the construction of the entire high-level synthesis system. The system has been successfully implemented in C++ and has proven to be reliable, expansible, and sufficiently fast.< >

关键词： hardware design languages High level synthesis Algorithm design and analysis Object oriented modeling Handicapped aids Design methodology Image analysis Data models Very large scale integration Process design

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FlexPath NP: a network processor concept with application-driven flexible processing paths 05

FlexPath NP: a network processor concept with application-dr...

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proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Rainer Ohlendorf Andreas Herkersdorf Thomas Wild Munich University of Technology Munich Germany

ISBN: (纸本)9781595931610

In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP) application sub-functions onto both SW programmable processor (CPU) resources and (re-)configurable HW building blocks, such that different packet flows are forwarded via different, optimized processing paths through the NP. Packets with well understood, relatively simple processing requirements may even bypass the central CPU complex (AutoRoute). In consequence, CPU processing resources are more effectively used and the overall NP performance and throughput are improved compared to conventional NP architectures. We present analytical performance estimations to quantify the performance advantage of FlexPath (expressed as available CPU instructions for each packet traversing the CPUs) and introduce a platform-based system on Programmable Chip (SoPC) based architecture which implements the FlexPath NP concept.

关键词： hardware accelerators application-specific architectures network processors dynamically reconfigurable processors IP networking

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