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proceedings of the IEEE international conference on Electronics, Circuits, and systems 1998年 1卷 85-88页

作者： Cardoso, Joao M.P. Neto, Horacio C. INESC Lisboa Portugal

This article describes a new approach to synthesize dedicated hardware from a system specification using the Java language. The new compiler named GALADRIEL starts from Java classfiles produced from the initial Java specification and processes the system information in order to exploit the concurrency implicit in each method, so that it can be efficiently implemented by multiple hardware and/or software components. The paper gives emphasis to the compiler techniques used to exploit the implicit concurrency and to the use of high-level synthesis to generate the hardware models from the Java bytecodes information.

关键词： Computer hardware

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Fuzzy controller on FPGA chip

Fuzzy controller on FPGA chip

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IEEE international conference on Fuzzy systems (FUZZ-IEEE)

作者： M.A. Manzoul D. Jayabharathi Department of Electrical Engineering Southem Illinois University Carbondale IL USA

A hardware implementation of fuzzy controllers on field programmable gate arrays (FPGAs) is described. FPGAs are semicustom integrated circuits that combine the attractive features of both programmable logic devices and gate arrays. software for synthesizing fuzzy controllers into Boolean equations was developed. The file that contains the set of Boolean equations is accepted directly by the development system of the FPGA. The development system then produces the necessary code for programming the FPGA chip. The speed of the fuzzy controller is determined by the response time of the FPGA circuit that realizes the Boolean equations. A speed of 50M FLIPS was achieved. The software together with the FPGA development system provide a complete design automation tool for fuzzy controllers.< >

关键词： Fuzzy control Field programmable gate arrays Programmable logic arrays Equations Automatic control hardware Application specific integrated circuits Programmable logic devices Control system synthesis Integrated circuit synthesis

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Synchronous methodology for designing hardware, software and mixed embedded systems

Synchronous methodology for designing hardware, software and...

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international conference on VLSI Design

作者： G. Berry Esterel Technologies TWINSI Villeneuve Loubet France

The tutorial presents the synchronous methodology for the design of hardware, software, or mixed embedded systems. This methodology was initially developed in the mid 80's in research, with the creation of synchronous languages such as Esterel, Lustre, or Signal. It became industrial in the 90's and is now used in a wide range of applications, from the design of safety-critical systems in avionics or automobile to the design and verification of complex electronic circuits and systems on Chip. We first present the basic cycle-based synchronous computation model and give a general overview of synchronous techniques, tools, and application areas. We explain why the synchronous approach makes design safer and verification simpler and we give industrial references. We then address the following technical issues: textual vs. graphical specification; sequencing, concurrency, and preemption; control path vs. data path; optimized hardware and software synthesis; formal verification of assertions and properties. We illustrate the topics by various examples, using the Esterel Studio system for demos. Finally, we show how synchronous techniques make it possible to generate hardware or software from the same specification and with the very same semantics, and how they fit in conventional hardware and software workflows.

关键词： Design methodology software design hardware Embedded software Embedded system Application software Electronics industry Aerospace electronics Automobiles Electronic circuits

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system testability evaluation with STA

System testability evaluation with STA

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international conference on Microelectronics, ICM

作者： W. Maroufi M. Marzouki LIP6 Laboratory Paris France

This paper presents a Computer Aided Testability tool named STA (system Testability Assistant), aimed at proposing a testability strategy for systems as early as possible in the design process. Given a system description, STA first compiles it in order to create system, boards, and circuits objects, and then proceeds bottom-up, from the circuit to the system, in order to evaluate the actual testability of the whole system, recommend a testability strategy and testability features inclusion in some modules, and provides support for including these testability features in the system by calling external generators or synthesis for testability tools.

关键词： Circuit testing system testing Circuit synthesis Costs Laboratories Process design software testing hardware software systems Modeling

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Control system architecture for integrated information technology facilities

Control system architecture for integrated information techn...

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Annual Hawaii international conference on system Sciences (HICSS)

作者： E.E. Roberts D.A. Chappell J.F. Nunamaker Department of Management Information Systems College of Business and Public Administration University of Arizona Tucson Tucson AZ USA

Corporations, universities and other institutions are seeking to provide unified environments that integrate computer hardware and software with advanced and traditional presentation technologies. These integrated information technology facilities (IITF) are often called Boardroom 2000, Classrooms of the Future, and the like. The need for these facilities is real, but these unified environments unfortunately, do not currently exist except as vendor specific approaches. Integrated control of the software and hardware technologies from a variety of vendors is nonexistent. The paper develops a Control system Architecture for the consistent interface between the presenter and the information and presentation equipment. Following a layered approach similar to the ISO Open systems Interconnection reference model, the primary components of the Control system Architecture are user interfaces, a Control system Processor, control network(s), and controlled equipment.< >

关键词： Control systems Information technology Control system synthesis Computer architecture hardware Process control Educational institutions software Centralized control ISO

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Automatic parallelism exploitation for FPL-based accelerators

Automatic parallelism exploitation for FPL-based accelerator...

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Annual Hawaii international conference on system Sciences (HICSS)

作者： J. Becker K. Schmidt Institute for Microelectronic Systems Darmstadt University of Technology Darmstadt Germany Daimler Benz Aerospace Ulm Germany

The paper introduces the first complete programming framework for coarse grain dynamically reconfigurable accelerators and their application development. It includes a general model for cooperating host/accelerator platforms and a parallelizing compilation technique derived from it. The paper is an introduction illustrating these techniques and their principles by examples: a machine architecture and its application development framework performing a "software-only" accelerator implementation (synthesis). The paper discusses the exploitation of four different levels of parallelism during this compilation process for achieving optimized speedups and hardware resource utilization.

关键词： Acceleration Circuits hardware Parallel processing Logic programming software tools Dynamic programming Reconfigurable logic Application software Fabrication

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Formal behavioural synthesis of Handel-C parallel hardware implementations from functional specifications

Formal behavioural synthesis of Handel-C parallel hardware i...

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Annual Hawaii international conference on system Sciences (HICSS)

作者： A.E. Abdallah J. Hawkins South Bank University London UK

Enormous improvements in efficiency can be achieved through exploiting parallelism and realizing implementation in hardware. On the other hand, conventional methods for achieving these improvements are traditionally costly, complex and error prone. Two significant advances in the past decade have radically changed these perceptions. Firstly, the FPGA, which gives us the ability to reconfigure hardware through software, dramatically reducing the costs of developing hardware implementations. Secondly, the language Handel-C with primitive explicit parallelism which can compile programs down to an FPGA. In this paper, we build on these recent technological advances and present a systematic approach of behavioural synthesis. Starting with an intuitive high level functional specification of a problem, given without annotation of parallelism, the approach aims at deriving an efficient parallel implementation in Handel-C, which is subsequently compiled into a circuit implemented on reconfigurable hardware. Algebraic laws are systematically used for exposing implicit parallelism and transforming the specification into a collection of interacting components. Formal methods based on data refinement and a small library of higher order functions are then used to derive behavioural description in Handel-C of each component. A small case study illustrates the use of this approach.

关键词： hardware Field programmable gate arrays Costs Algorithm design and analysis Circuit synthesis Application software High level languages Programming profession Art Functional programming

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From algorithm graph specification to automatic synthesis of FPGA circuit: a seamless flow of graphs transformations

From algorithm graph specification to automatic synthesis of...

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13th international conference on Field-Programmable Logic and Applications (FPL 2003)

作者： Kaouane, L Akil, M Sorel, Y Grandpierre, T Lab A2SI Grp ESIEE F-93162 Noisy Le Grand France Inst Natl Rech Informat & Automat OSTRE F-78153 Le Chesnay France

ISBN: (纸本)3540408223

The control, signal and image processing applications are complex in terms of algorithms, hardware architectures and real-time/embedded constraints. system level CAD softwares are then useful to help the designer for prototyping and optimizing such applications. These tools axe oftently based on design flow methodologies. This paper presents a seamless design flow which transforms a data dependence graph specifying the application into an implementation graph containing both data and control paths. The proposed approach follows a set of rules based on the RTL model and on mechanisms of synchronized data transfers in order to transform automatically the initial algorithmic graph into the implementation graph. This transformation flow is part of the extension of our AAA (Algorithm-Architecture Adequation) rapid prototyping methodology to support the optimized implementation of real-time applications on reconfigurable circuits. It has been implemented in SynDEx(1), a system level CAD software tool that supports AAA.

关键词： Field programmable gate arrays (FPGA)

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A theory of combinational programs

A theory of combinational programs

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Asia-Pacific conference on software Engineering

作者： T. Van Dung H. Jifeng International Institute for Software Technology United Nations University Macao China

ISBN: (纸本)0769514081

The actual behaviour of a hardware device available for an implementation of a control system can be simulated by a program, allowing the hardware device to be proved correct by standard software techniques. In this paper we formalise event semantics of hardware description language in the form of relations and use relation calculus to prove properties (including termination, stability, and uniqueness of final state) of combinational programs, the cycle behaviour of which is defined as a conditional loop of non-deterministic choices between generalised parallel assignments.

关键词： hardware design languages Computational modeling Helium Control system synthesis software standards Calculus Stability Discrete event simulation Wires Registers

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A transmission model for hardware-in-the-loop powertrain control system software development

A transmission model for hardware-in-the-loop powertrain con...

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IEEE conference on Control Technology and Applications (CCTA)

作者： L. Mianzo Advanced Energy Transformation Systems Visteon Automotive Systems Dearborn MI USA

Powertrain control systems engineers are increasingly being asked to deliver high quality products faster, under stricter emissions and fuel economy regulations as well as meet higher customer expectations. In order to meet these demands, control engineers are turning to computer-aided tools that support rapid development of quality products, such as hardware-in-the-loop (HIL) systems. In the paper, a transmission model that has been developed for the Visteon Powertrain HIL Project is described. The transmission model is used to verify the on-board diagnostics (OBD-II) and transmission control logic.

关键词： Power system modeling Mechanical power transmission Control system synthesis system software Logic Gears Torque system testing Control systems Open loop systems

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