Bluespec system Verilog is an EDL toolset for ASIC and FPGA design offering significantly higher productivity via a radically different approach to high-level synthesis. Many other attempts at high-level synthesis hav...
ISBN:
(纸本)9780780385092
Bluespec system Verilog is an EDL toolset for ASIC and FPGA design offering significantly higher productivity via a radically different approach to high-level synthesis. Many other attempts at high-level synthesis have tried to move the design language towards a more software-like specification of the behavior of the intended hardware. By means of code samples, demonstrations and measured results, we illustrate how Bluespec system Verilog, in an environment familiar to hardware designers, can significantly improve productivity without compromising generated hardware quality.
This paper presents the computer control system for the NRC fretting test rig. The fretting test rig and the hardware and software of the control systems are briefly described. The system's modeling and controller...
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This paper presents the computer control system for the NRC fretting test rig. The fretting test rig and the hardware and software of the control systems are briefly described. The system's modeling and controller design are given. Experimental results are presented to demonstrate the performance of the designed computer control system.< >
The voter, as the key component in either multi-model group system in the field of industry control or in the group decision support system, is the guarantee of efficiency of whole work and reliability. In the common ...
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ISBN:
(纸本)0780384032
The voter, as the key component in either multi-model group system in the field of industry control or in the group decision support system, is the guarantee of efficiency of whole work and reliability. In the common situation, the voter can be realized by the pure-software. However, in the comparatives rigid industry-control field, especially in the group control or decision in distance under internet environment, the voter is easy to be interfered by the electromagnetism, even computer virus or hacker program and system has some degree of patient danger. On the other hand, in some situations of high requirement of responsible time, such as instant control system in the electronic net, prediction of short time charge in electronic system and adjustable decision system, software voter model is hard to meet the requirement of system velocity. hardware voter, however, based on the hardware logic model, has much more advantage in the velocity and reliability than software one.
The proceedings contain 120 papers. The special focus in this conference is on Computer Aided systems Theory. The topics include: Solving a real–world FAP using the scatter search metaheuristic;on the success rate of...
ISBN:
(纸本)9783642047718
The proceedings contain 120 papers. The special focus in this conference is on Computer Aided systems Theory. The topics include: Solving a real–world FAP using the scatter search metaheuristic;on the success rate of crossover operators for genetic programming with offspring selection;on structural identification of 2d regression functions for indoor bluetooth localization;grid-enabled mutation-based genetic algorithm to optimise nuclear fusion devices;priority rule generation with a genetic algorithm to minimize sequence dependent setup costs;a grasp–vns hybrid for the fuzzy vehicle routing problem with time windows;performance modelling for avionics systems;object-oriented petri nets-based modeling of resources in project engineering;simulation based design of control systems using devs and petri nets;learning autonomous helicopter flight with evolutionary reinforcement learning;Transforming UML-based system descriptions into simulation models as part of system development frameworks;model-based design and verification of reactive systems;resonant tunnelling diode-based circuits: Simulation and synthesis;a practical methodology for integration testing;safety oriented laparoscopic surgery training system;Co-operative extended kohonen mapping (EKM) for wireless sensor networks;morphotronic system applications;sniper: A wireless sensor network simulator;embedded fortress –software environment for intellectual property protection in embedded systems;collaborative xml document versioning;designing communication space in wireless sensor network based on relational attempt;parallel distributed genetic algorithm for expensive multi-objective optimization problems;boundary scan security enhancements for a cryptographic hardware;automated design of totally self-checking sequential circuits;a general purpouse control system;on the first exit time problem for a gompertz-type tumor growth;diffusion processes subject to catastrophes;preface.
CSP (communicating sequential processes) is a useful algebraic notation for creating a hierarchical behavioral specification for concurrent systems, due to its formal interprocess synchronization and communication sem...
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ISBN:
(纸本)9780769519234
CSP (communicating sequential processes) is a useful algebraic notation for creating a hierarchical behavioral specification for concurrent systems, due to its formal interprocess synchronization and communication semantics. CSP specifications are amenable to simulation and formal verification by model-checking tools. To overcome the drawback that CSP is neither a full-featured nor popular programming language, an approach called "selective formalism" allows the use of CSP to be limited to specifying the control portion of a system, while the rest of its functionality is supplied in the form of C++ modules. These are activated through association with abstract events in the CSP specification. The target system is constructed using a framework called CSP++, which automatically translates CSP specifications into C++, thereby making CSP directly executable. Thus a bridge is built that allows a formal method to be combined with a popular programming language. It is believed that this methodology can be extended to hardware/softwarecodesign.
The EE department at Penn State has recently developed a practice-oriented Rapid system Prototyping course. Emphasizing language-based topdown design, many of the course topics and techniques parallel those developed ...
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ISBN:
(纸本)0769503128
The EE department at Penn State has recently developed a practice-oriented Rapid system Prototyping course. Emphasizing language-based topdown design, many of the course topics and techniques parallel those developed under the DoD RASSP program. The course was augmented by extensive use of CD-ROM and WWW resources;in particular, selections from the RASSP Education and Facilitation (E&F) instructional modules were used in-class, and many more RASSP modules were assigned in the readings. This paper briefly describes our experiences with this course, and with the RASSP modules as a supplement to conventional class materials.
According to the principle of FIR filter, we firstly design and simulate the model file with DSP Builder in the environment of Matlab/Simulink. Secondly, we transform this model file to VHDL source codes with Signal-C...
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According to the principle of FIR filter, we firstly design and simulate the model file with DSP Builder in the environment of Matlab/Simulink. Secondly, we transform this model file to VHDL source codes with Signal-Compiler and implement processes of analysis, synthesis and adaptation in Quartus II. At last, we create a SOPC system-NiosII, where FIR filter arithmetic can be generated to a custom instruction. Till now, the hardware-software co-design of FIR filter arithmetic has been completed.
The synthesis problems of intelligent control models for a belt conveyor with a variable lifting angle are considered. The models take into account the acting forces, uneven loading and control actions. A complex crit...
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We present a two step synthesis approach to the design of VLSI fuzzy controllers. First, we derive a VHDL description of the ASIC from the problem specifications, the hardware constraints and the performance requireme...
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We present a two step synthesis approach to the design of VLSI fuzzy controllers. First, we derive a VHDL description of the ASIC from the problem specifications, the hardware constraints and the performance requirements. Then, we map the VHDL description to gate level description with a standard logic synthesis tool. The process is repeated until the resulting design is tuned to the global requirements of the control device in terms of performance and cost.< >
Embedded systems in exoskeletons and wearable rehabilitation devices require efficient monitoring of human gait with stringent demands for real-time and reliable performance. Gait trajectory prediction enables full-pr...
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ISBN:
(纸本)9798400702891
Embedded systems in exoskeletons and wearable rehabilitation devices require efficient monitoring of human gait with stringent demands for real-time and reliable performance. Gait trajectory prediction enables full-process perception of future gait patterns. The template matching approach is a promising algorithm for gait trajectory prediction. However, it has challenges in terms of template selection and dynamic stability. We developed DTW-KM Template Selection Method using the DTW distance matrix and K-means to find trajectories with generality and diversity as candidate templates. In addition, we use a matching method combining soft constraints and quadratic weighting, named ScW Template Matching Method. it can balance timeliness, stability and flexibility, and suppress gait phase and trajectory oscillations. Preliminary experimental results show that our method achieves stable prediction of 0.5--1s gait using efficient inference on embedded devices.
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