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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

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Embedded systems Week 2010 - proceedings of the 8th IEEE/ACM/IFIP international conference on Compilers, Architecture and synthesis for Embedded systems, CODES+ISSS'2010: Foreword

Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM...

引用

Embedded systems Week 2010 - proceedings of the 8th IEEE/ACM/IFIP international conference on Compilers, Architecture and synthesis for Embedded systems, CODES+ISSS'2010 2010年 iii页

作者： Givargis, Tony Donlin, Adam

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Model driven engineering for SoC co-design

Model driven engineering for SoC co-design

引用

Annual IEEE Northeast Workshop on Circuits and systems (NEWCAS)

作者： J. Dekeyser P. Boulet P. Marquet S. Meftali Laboratoire dInformatique Fondamentale de Lille Université des Sciences et Technologies de Lille Villeneuve d'Ascq France

SoC co-design requires to master a lot of different abstraction levels, different simulation techniques, different synthesis tools. Due to the evolution of the technologies, the best one is the one to come. Evolution of an embedded system both hardware and software, is not simple. The business logic has to be kept and the technical aspect has to be thrown. To improve the permanence of system on chip we have to abstract from the technical concerns. Model driven engineering (MDE) proposes a separation of concerns: application and technical concerns. The use of a modeling standard can capitalize system descriptions and improve system evolution and integration. A particular aspect of MDE concerns model transformations and code generation. At this level, the basic model driven architecture pattern involves the definition of a platform-independent model (PIM) and its automated mapping to one or more platform-specific models (PSMs). By defining different PIM and PSM dedicated to embedded systems, we show the benefits of using the MDE approach in system on chip codesign. From UML 2.0 profiles to systemC or VHDL codes, the same model transformation engine is used with different rules expressed in XML.

关键词： Model driven engineering Embedded system system-on-a-chip hardware Embedded software Logic Application software Unified modeling language Engines XML

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High-level synthesis for large bit-width multipliers on FPGAs: a case study 05

High-level synthesis for large bit-width multipliers on FPGA...

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proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Gang Quan James P. Davis Siddhaveerasharan Devarkal Duncan A. Buell University of South Carolina Columbia SC

ISBN: (纸本)9781595931610

In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are required for cryptography and error correction circuits for more secure and reliable transmissions over highly insecure and/or noisy channels in networking and multimedia applications. The design space for these circuits is very large when integer multiplication on large operands is carried out hierarchically. In this paper, we explore automated synthesis of high bit-width unsigned integer multiplier circuits by defining and validating an estimator function used in search and analysis of the design space of such circuits. We focus on analysis of a hybrid hierarchical multiplier scheme that combines the throughput advantages of parallel multipliers and the resource cost-effectiveness of serial ones. We present an analytical model that rapidly predicts timing and resource usage for selected model candidates. We evaluate the estimator model in the design of a practical application, a 256-bit elliptic curve adder implemented on a Xilinx FPGA fabric. We show that our estimator allows implementation of fast, efficient circuits, where resultant designs provide order-of-magnitude performance improvements when compared with that of software implementations on a high performance computing platform.

关键词： reconfigurable computing large-scale integer multipliers FPGA devices high level synthesis design exploration

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A user-friendly manufacturing system for 'hyper-environments'

A user-friendly manufacturing system for 'hyper-environments...

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IEEE international conference on Robotics and Automation (ICRA)

作者： M. Mitsuishi S. Warisawa Y. Hatamura T. Nagao B. Kramer Department of Engineering Synthesis Faculty of Engineering University of Tokyo Tokyo Japan Department of Civil Mechanical and Environmental Engineering George Washington University DC USA

The authors describe a manufacturing system that allows the natural manipulation of tools of production and raw materials in environments which cannot be accessed directly by normal human senses. The term 'hyper-environment' connotes such an environment as remote locations, the micrometer world, or outer space. The authors discuss the functions necessary to realize the system, the software and hardware employed in the system, and the 'reality communication' techniques needed to allow the remote human operator to monitor the operation effectively. Attention is given to a technique for transforming cutting force information into auditory information that allows the operator to determine the cutting conditions. Tests in which a machining center in Tokyo was controlled by teleoperators in Washington are described.< >

关键词： Manufacturing systems Humans Production systems Raw materials Communication system software software systems hardware Remote monitoring Testing Milling machines

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COWLS: hardware-software co-synthesis of distributed wireless low-power embedded client-server systems

COWLS: hardware-software co-synthesis of distributed wireles...

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international conference on VLSI Design

作者： R.P. Dick N.K. Jha Department of Electrical Engineering Princeton University Princeton NJ USA

In this paper we present a hardware-software co-synthesis algorithm, called COWLS, which targets embedded system composed of servers and low-power clients which communicate with each other through a channel of limited bandwidth, e.g., a wireless link. Clients may be mobile. COWLS allows both hard and soft real-time constraints. It simultaneously optimizes the price of the client-server system, the power consumption of the client, and the response times of tasks which have only soft deadlines, while meeting all the hard deadlines. It produces numerous solutions which trade off different architectural features, e.g., price, power consumption, and response time, of an embedded client-server system. As far as we know, this is the first co-synthesis algorithm of its kind. We present experimental results of synthesizing a low power, client-server camera system as well as several randomized examples.

关键词： Client-server systems Energy consumption Embedded system Iterative algorithms Bandwidth Delay Batteries Wire Cameras Consumer products

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A structured approach to embedded control systems implementation

A structured approach to embedded control systems implementa...

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IEEE conference on Control Technology and Applications (CCTA)

作者： J.F. Broenink G.H. Hilderink Control Laboratory Faculty EE University of Twente Enschede Netherlands

The method presented aims at supporting the development of control software for embedded control systems. The method considers the implementation process as a stepwise refinement from physical system models and control laws to efficient control computer code, and that all phases are verified by simulation. Simulation is also used as a verification tool during physical system modeling and control law development. Data flow diagrams are used to describe the control software throughout the whole implementation process. Since we aim at heterogeneous distributed processors as target hardware, we use a link driver library based on the CSP channel concept. Communication peculiarities are encapsulated by the link drivers.

关键词： Control systems Embedded software Home appliances Control system synthesis Computational modeling Communication system control Embedded system Vehicle dynamics hardware software systems

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Multi-level communication synthesis of heterogeneous multilanguage specification

Multi-level communication synthesis of heterogeneous multila...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： F. Hessel P. Coste G. Nicolescu P. LeMarrec N. Zergainoh A. Jerraya TIMA Laboratory Grenoble France

The complexity of modern embedded systems requires the cooperation of several teams belonging to different cultures and using different languages as well as the reuse of software, hardware and communication IP modules at the early design steps. The key issue for the design of such systems is the overall system validation and the synthesis of the communication between the different subsystems. In this paper we focus on the problem of multi-level communication synthesis and show the results of the application of this methodology on an example. Designers get feedback at all design steps via the cosimulation engine that permits fast evaluation.

关键词： Object oriented modeling Embedded system Time to market Design methodology Wires Access protocols Switches Laboratories Computer science hardware

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SoC synthesis with automatic hardware-software interface generation

SoC synthesis with automatic hardware-software interface gen...

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international conference on VLSI Design

作者： A. Singh A. Chhabra A. Gangwar B.K. Dwivedi M. Balakrishnan A. Kumar Tejas Networks India Private Limited Bangalore India STMicroelectronics Private Limited Noida India Department of Computer Science & Engineering Indian Institute of Technology New Delhi India

Design of efficient system-on-chips (SoCs) requires thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardware in order to meet the cost as well as the performance constraints. However, faster time to market requires automation of synthesis of these code segments of the application from high level specification such as C along with its interfaces. Such a synthesis system should be able to generate hardware which is easily pluggable in various types of architectures, as well as augment the application code to automatically take advantage of this new hardware component. In this paper, we address this problem and present an approach for complete SoC synthesis. We automatically generate synthesizable VHDL for the compute intensive part of the application along with necessary interfaces. Our approach is generic in the sense that it supports various processors and buses by keeping a generic hardware interface on one end and a dedicated one on the other. The generated hardware can be used in a tightly or loosely coupled manner in terms of memory and register communication. We present the effectiveness of this approach for some commonly used image processing spatial filter applications.

关键词： hardware system-on-a-chip Costs Time to market Automation Computer architecture Computer interfaces Registers Image processing Spatial filters

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hardware/software co-training by FPGA/ASIC synthesis and programming of a RISC microprocessor-core

Hardware/software co-training by FPGA/ASIC synthesis and pro...

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IEEE international conference on Microelectronic systems Education

作者： J.E. Becker C. Bieser A. Thomas K.D. Muller-Glaser J. Becker Institut für Technik der Informationsverarbeitung Universität Karlsruhe Germany

ISBN: (纸本)0769519733

This paper describes the combination of educating both, hardware and software with one practical lab. The needs to offer such a co-training concept are brought out by the demands of industry towards the desired skills of today's engineers. An engineer's view must no longer be restricted to his/her own work, but has to be widened to a complete system view. To provide an appropriate education scheme the university courses have to adapt to these changes. Therefore an innovative lab concept is presented here. Its goal is to improve students skills not only in a single direction, but to deliver an efficient inter disciplinary hardware software lab course, combined with training state-of-the-art industrial architectures and relevant tools.

关键词： hardware Field programmable gate arrays Application specific integrated circuits Reduced instruction set computing software design Programming profession Industrial training Computer industry Electronic mail software tools

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Concurrent embedded real-time software verification

Concurrent embedded real-time software verification

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IEEE Annual international Computer software and Applications conference (COMPSAC)

作者： Pao-Ann Hsiung Institute of Information Science Academia Sinica Taiwan

The verification of software is more complex than hardware due to inherent flexibilities (dynamic behavior) that incur a multitude of possible system states. The verification of Concurrent Embedded Real-Time software (CERTS) is all the more difficult due to its concurrency and embeddedness. The work presented shows how the complexity of CERTS verification can be reduced significantly through answering common engineering questions such as when, where, and how one must verify embedded software. Application examples illustrate the usefulness of our technique in increasing verification scalability.

关键词： Embedded software Concurrent computing Processor scheduling Control system synthesis Scalability software systems Embedded computing Information science Formal verification Real time systems

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