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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

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A codesign case study: implementing arithmetic functions in FPGAs

A codesign case study: implementing arithmetic functions in ...

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international conference and Workshop on Engineering of Computer-Based systems

作者： I.V. Klotchkov S. Pedersen Department of Information Technology Technical University of Denmark Lyngby Denmark

Different ways of implementing and designing arithmetic functions for 16/32 bit integers in FPGA technology are studied. A comparison of four different design methods is also included. The results are used to increase the overall system performance in a dedicated 3D image analysis prototype system by moving a vector length calculation from software to hardware. The conclusion is that by adding one relatively simple board containing two FPGAs in the prototype setup, the total computing time is reduced by 30%. The total amount of image data, in this case 300 Mbyte, which has to be transmitted via the network is reduced by a factor of two, and the required network bandwidth is reduced similarly.

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Implementing C designs in hardware: a full-featured ANSI C to RTL Verilog compiler in action

Implementing C designs in hardware: a full-featured ANSI C t...

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IEEE international conference on Verilog HDL

作者： D. Soderman Y. Panchul CompiLogic Corporation San Jose CA USA

The usage of a new full-featured ANSI C to synthesizable RTL Verilog compiler for implementing system-level algorithms in hardware is described. The compiler automatically creates multiple Verilog state machines for loops, on-chip register and arithmetic macros, and external memory interfaces. A two-pass compile interfacing with a synthesis tool allows insertion of registers and wait states to balance propagation delays for maximum performance. This design methodology is demonstrated using several compression-decompression, prime number, and sorting algorithms. Compiled RTL Verilog designs have been synthesized into FPGAs and ASICs. The compression-decompression algorithm executes in nearly one quarter the clock cycles using hardware versus software on a PentiumPro. This cycle efficiency is due to variable storage in simple registers, clock packing techniques, and functional level parallelism. Efficient clock packing is demonstrated with a prime number generator algorithm which executes in 25x fewer clock cycles compared to Pentium software execution.

关键词： hardware design languages Clocks Field programmable gate arrays software algorithms Registers Arithmetic Design methodology Sorting Timing Propagation delay

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Xfuzzy: a design environment for fuzzy systems

Xfuzzy: a design environment for fuzzy systems

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IEEE international conference on Fuzzy systems (FUZZ-IEEE)

作者： D.R. Lopez C.J. Jimenez I. Baturone A. Barriga S. Sanchez-Solano Centro Informático Científico de Andalucía Seville Spain Centro Nacional de Microelectrónica Instituto de Microelectrónica de Sevilla (IMSE-CNM) Seville Spain

Xfuzzy is a CAD tool that eases the development of fuzzy systems from their conception to their final implementation. It is composed of a set of modules and programs that share a common specification language and cover the different stages of the design process. Modules for describing, verifying and tuning the behavior of the system are integrated within the environment. In addition to these features, common to other fuzzy design tools, a relevant characteristic of Xfuzzy is that it includes several synthesis facilities for implementing the system on either software or hardware.

关键词： Fuzzy systems hardware Fuzzy logic Libraries Control system synthesis Fuzzy sets Design automation Specification languages Process design software systems

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3rd international Workshop on Tools and Algorithms for the Construction and Analysis of systems, TACAS 1997

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3rd international Workshop on Tools and Algorithms for the Construction and Analysis of systems, TACAS 1997

ISBN: (纸本)3540627901

The proceedings contain 28 papers. The special focus in this conference is on Space Reduction Techniques and Space Reduction Techniques. The topics include: hardware and software synthesis, optimization, and verification from esterel programs;combining partial order and symmetry reductions;space efficient reachability analysis through use of pseudo-root states;the reference component of pep;a tool to support formal reasoning about computer languages;the term processor generator kimwitu;the unifying power of polymorphism;a tableau system for linear-time temporal logic;model-checking for a subclass of event structures;fictitious clock as an abstraction of dense time;a flexible toolset for monadic second-order logic;a brief introduction to coloured petri nets;formal verification of statecharts with instantaneous chain reactions;compositional state space generation from lotos programs;syntactic detection of process divergence and non-local choice in message sequence charts;an automata based verification environment for mobile processes;compositional performance analysis;incremental development of deadlock-free communicating systems;automatic synthesis of specifications from the dynamic observation of reactive programs;visual verification of reactive systems;theorem prover support for the refinement of stream processing functions;tables, types, and model checking;test generation for intelligent networks using model checking;mechanically verified self-stabilizing hierarchical algorithms and the bounded retransmission protocol must be on time.

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IBM AS/400 processor architecture and design methodology

IBM AS/400 processor architecture and design methodology

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Q.G. Schmierer A.H. Wottreng IBM Application Business Systems Division Rochester MN USA

The IBM AS/400 is a family of general purpose mid-range computers specifically designed to run commercial business applications and transaction processing in batch and interactive environments. The April, 1991 announcement is the second generation of the system. It provides a 2.7 times performance improvement over its predecessor. Architectural support for multiprocessors is also part of the product. Achieving this performance improvement required significant changes to the processor architecture, chip technologies and operating system hardware. The architecture and design methodology used in the IBM AS/400 processor are briefly described. The processor chip designs made extensive use of high level hardware description languages and logic synthesis. Each design group was responsible for defining its design in VHDL and converting the design into logic using logic synthesis. The designer's experiences with these new methods are highlighted.< >

关键词： Design methodology Logic design Application software Business Operating systems hardware CMOS logic circuits CMOS technology Packaging Clocks

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The Tension between Integration and Fragmentation in a Component Based software Development Ecosystem

The Tension between Integration and Fragmentation in a Compo...

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Annual Hawaii international conference on system Sciences (HICSS)

作者： J. Arndt J. Dibbern University of Mannheim Germany

Historically, software application systems have been produced either individually tailored for the specific customer, or they have been adapted from standardized packages. This paper proposes that component based software development could provide a synthesis of both approaches, combining the best aspects of each of the other two paradigms. Taking a closer look at the underlying principles of software reuse and modularity, however, reveals a number of conflicting forces that influence the acceptance and diffusion of this new paradigm within and throughout the software industry. A dialectical change perspective is used to explain this change process. It is argued that traditional software producers have a dominant position in their industry, and will be able to retain this position for some time. However, the concept of mindful innovation is introduced to give an outlook how smaller software producers might exploit the opportunities that this paradigm shift provides.

关键词： Programming Ecosystems Computer industry Application software hardware Productivity software systems software packages Packaging Technological innovation

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systemoprh: dynamic/online/adaptive system-level optimization for SoC

SysteMoprh: dynamic/online/adaptive system-level optimizatio...

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international conference on High Performance Computing in the Asia-Pacific Region

作者： N. Yoshimatsu M. Yoshida T. Soga M. Shuto Y. Tanoue Y. Fujii K. Eshima T. Hayashidai K. Murakami Fukuoka Industry Japan Fukuoka Industry Science & Technology Foundation Japan Institute of Systems & Information Technologies/KYUSHU Department of Informatics Kyushu University Japan Department of Informatics Kvushu University

This work describes systemorph, a feedback directed dynamic, online and adaptive hardware/instruction set architecture (JSA)/software co-optimization technology. The technology enables to optimize performance, power, and consumption energy for a system dynamically. We describe systemorphs elemental technologies those are an online profiling, a dynamic adaptive optimization and a smart hardware. Functionality morphing is one of the systemorph implementations for a system which consists of processor and reconfigurable logic. It reconfigures hardware dynamically then rewrites software to utilize the reconfigured hardware online. We demonstrated the systemorph on a reconfigurable processor by implementing functionality morphing. Online profiling, online synthesis, and binary rewriting are implemented and verified on the prototypal system. Then we propose a processor suitable implementing systemorph using a VUW execution unit.

关键词： Adaptive systems hardware Energy consumption Feedback Computer architecture Reconfigurable logic Prototypes VLIW Application software Computer industry

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software synthesis through task decomposition by dependency analysis 96

Software synthesis through task decomposition by dependency ...

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proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

作者： Youngsoo Shin Kiyoung Choi School of Electrical Engineering Seoul National University Seoul Korea 151-742

ISBN: (纸本)9780818675973

Latency tolerance is one of main problems of software synthesis in the design of hardware-software mixed systems. This paper presents a methodology for speeding up systems through latency tolerance which is obtained by decomposition of tasks and generation of an efficient scheduler. The task decomposition process focuses on the dependency analysis of system i/o operations. Scheduling of the decomposed tasks is performed in a mixed static and dynamic fashion. Experimental results show the significance of our approach.

关键词： scheduler CDFG dependency software synthesis thread

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hardware allocation in FIDIAS system

Hardware allocation in FIDIAS system

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CompEuro

作者： J. Septien D. Mozos F. Tirado R. Hermida A. Sotelo Departamento de Informática y Automática Universidad Complutense de Madrid Madrid Spain

A system oriented to the design of the datapath and the control of a digital system from a behavioral description and written in a high-level language is presented. The system module charged with the subtask of datapath allocation is shown in detail. The source code for this project is written in C language and runs on an HP9000/300 workstation under HP-US. GKS and X-Windows standards are used for graphics display and user interaction.< >

关键词： hardware Automatic generation control Displays Graphics Multiplexing Digital control Control system synthesis Data systems Workstations Digital systems

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High-level synthesis of nonprogrammable hardware accelerators

High-level synthesis of nonprogrammable hardware accelerator...

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international conference on Application Specific systems (ASAP), Architectures and Processors

作者： R. Schreiber S. Aditya B. Ramakrishna Rau V. Kathail S. Mahlke S. Abraham G. Snider Hewlett Packard Company Palo Alto CA USA

The PICO-N system automatically synthesizes embedded nonprogrammable accelerators to be used as co-processors for functions expressed as loop nests in C. The output is synthesizable VHDL that defines the accelerator at the register transfer level (RTL). The system generates a synchronous array of customized VLIW (very-long instruction word) processors, their controller local memory, and interfaces. The system also modifies the user's application software to make use of the generated accelerator. The user indicates the throughput to be achieved by specifying the number of processors and their initiation interval. In experimental comparisons, PICO-N designs are slightly more costly than hand-designed accelerators with the same performance.

关键词： High level synthesis hardware Acceleration Control system synthesis Coprocessors Registers Synchronous generators VLIW Automatic generation control Process control

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