检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,497 篇 会议
55 篇 期刊文献

馆藏范围

1,552 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

798 篇 工学
- 737 篇 计算机科学与技术...
- 559 篇 软件工程
- 153 篇 电气工程
- 135 篇 电子科学与技术（可...
- 103 篇 信息与通信工程
- 74 篇 控制科学与工程
- 22 篇 机械工程
- 13 篇 动力工程及工程热...
- 11 篇 光学工程
- 10 篇 建筑学
- 9 篇 仪器科学与技术
- 9 篇 生物工程
- 8 篇 材料科学与工程（可...
- 8 篇 土木工程
- 8 篇 生物医学工程（可授...
- 7 篇 安全科学与工程
- 6 篇 航空宇航科学与技...
179 篇 理学
- 104 篇 数学
- 48 篇 系统科学
- 39 篇 物理学
- 16 篇 统计学（可授理学、...
- 9 篇 生物学
- 6 篇 化学
108 篇 管理学
- 89 篇 管理科学与工程(可...
- 29 篇 工商管理
- 23 篇 图书情报与档案管...
15 篇 法学
- 11 篇 社会学
5 篇 经济学
- 5 篇 应用经济学
5 篇 教育学
- 5 篇 教育学
5 篇 医学
- 5 篇 临床医学
4 篇 艺术学
1 篇 农学

主题

359 篇 hardware
177 篇 computer archite...
162 篇 embedded system
135 篇 application soft...
87 篇 field programmab...
83 篇 embedded systems
75 篇 control system s...
69 篇 costs
67 篇 high level synth...
65 篇 computational mo...
65 篇 algorithm design...
64 篇 system-on-a-chip
63 篇 permission
62 篇 embedded softwar...
61 篇 real time system...
52 篇 timing
50 篇 system-on-chip
48 篇 computer science
47 篇 energy consumpti...
46 篇 space exploratio...

机构

10 篇 department of el...
8 篇 univ calif river...
8 篇 center for embed...
6 篇 school of comput...
6 篇 arizona state un...
6 篇 center for embed...
6 篇 department of co...
5 篇 princeton univ d...
5 篇 school of inform...
5 篇 department of co...
5 篇 philips research...
5 篇 institute for in...
5 篇 technische unive...
4 篇 department of el...
4 篇 ibm thomas j. wa...
4 篇 imec leuven
4 篇 politecn torino ...
4 篇 university of er...
4 篇 tu braunschweig
4 篇 university of do...

作者

9 篇 sri parameswaran
9 篇 ogras umit y.
9 篇 parameswaran sri
9 篇 nikil dutt
7 篇 rolf ernst
7 篇 dick robert p.
7 篇 dutt nikil
7 篇 robert p. dick
7 篇 leupers rainer
7 篇 vahid f
6 篇 jiang wei
6 篇 greg stitt
6 篇 teich juergen
6 篇 mitra tulika
6 篇 rainer leupers
6 篇 andreas gerstlau...
6 篇 a. sangiovanni-v...
6 篇 r. ernst
6 篇 jha niraj k.
5 篇 sungjoo yoo

语言

1,545 篇 英文
5 篇 其他
2 篇 中文

检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1552 条记录，以下是1431-1440 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Automatic component matching using forced simulation

Automatic component matching using forced simulation

引用

international conference on VLSI Design

作者： P.S. Roop A. Sowmya S. Ramesh School of Computer Science and Engineering University of New South Wales Sydney NSW Australia Department of Computer Science and Engineering Indian Institute of Technology Bombay India

Component-based synthesis of embedded systems will lead to the reuse of a vast library of hardware and software components and also facilitate rapid prototyping. However it is still low key, a primary reason being the lack of a systematic attempt at the development of automatic component matching algorithms. The main task of such an algorithm is to map a design function to a device from a library of system-level components. In this paper we propose a novel notion of simulation called forced simulation to formalize the correspondence between a function and a device. What distinguishes forced simulation from other techniques is the idea of forcing via an external interface, which can be automatically synthesized, and is useful for adapting the system level component to the given design functionality. We propose a new component matching algorithm based enforced simulation and illustrate it via the example of mapping a lathe controller port to Intel 82C55 in mode 2.

关键词： hardware Embedded system Control system synthesis Computational modeling Australia Prototypes Read only memory Logic devices software libraries Digital control

来源：评论

学校读者我要写书评

暂无评论

APECS code synthesis: Extending ocarina for multi-threaded code synthesis from AADL models for Safety Critical applications

APECS code synthesis: Extending ocarina for multi-threaded c...

引用

IEEE international conference on Networking, Sensing and Control

作者： Matthew Anderson Sandeep K. Shukla Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA

For Safety Critical CPS applications, Architecture Analysis and Design Language (AADL) can provide a framework for formally modeling end-to-end Cyber Physical systems (CPS). Such a model includes hardware platform model, software architecture model, the real-time bounds on software and hardware components. An AADL model of the system allows early formal analysis of real-time schedulability, end-to-end performance, power, memory requirements and correctness. Multiple tool support for AADL modeling and analysis exists, including software code generator, which glues together software components declared in the software architecture model. Ocarina is one such tool for software generation but it requires that the modeler provides the subprogram code in C/C++ or Ada. For correct-by-construction code synthesis, it is ideal to eliminate manually written code, and instead of using Ocarina as a glue code generator, using it for complete code synthesis from formal models. Support for Esterel and Lustre based specification of subprograms already have been attempted, but they usually specify specific subprogram elements, and the specific code generators are invoked to synthesis C/C++ code and then Ocarina glues them together based on the architectural constraints specified in the AADL model. This means that in a multi-threaded or multi-process software architecture, we still have to maneuver to get correct synchronization code. Moreover, if the granularity of code synthesis is at the function or subprogram level, we cannot gain much towards the goal of correct-by-construction synthesis and we believe that taking advantage of polychronous modeling and code synthesis would be ideal to achieve that goal. In this work, we show how to extend the Ocarina code generator to work with our Polychronous modeling and code synthesis solution to obtain multi-threaded code, improving the code-synthesis granularity from subprograms to processes while guaranteeing the implementation correctness.

关键词： Analytical models Process control Manuals Generators Synchronization Standards Context

来源：评论

学校读者我要写书评

暂无评论

Execution-time profiling for multiple-process behavioral synthesis

Execution-time profiling for multiple-process behavioral syn...

引用

IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： J.K. Adams J.A. Miller D.E. Thomas Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

This paper presents a technique for back-annotating the results of high-level synthesis into the source description to produce a timing-accurate behavioral simulation model. The resulting simulation model exhibits the same cycle-by-cycle behavior as a register-transfer level model, but can be simulated in a fraction of the time. This idea has analogies both to software profiling and to back-annotation at lower levels of hardware design. Experimental results demonstrate that the annotated behavioral simulation models run two to three orders of magnitude faster than register-transfer level simulation models, and only about an order of magnitude slower than behavioral models with no timing information.

关键词： Delay Control system synthesis Computational modeling Timing Discrete event simulation High level synthesis Signal synthesis Computer simulation hardware Performance analysis

来源：评论

学校读者我要写书评

暂无评论

synthesis-driven exploration of pipelined embedded processors

Synthesis-driven exploration of pipelined embedded processor...

引用

international conference on VLSI Design

作者： P. Mishra A. Kejariwal N. Dutt Architectures and Compilers for Embedded Systems (ACES) Laboratory Center for Embedded Computer Systems University of California Irvine CA USA

Recent advances on language based software toolkit generation enables performance driven exploration of embedded systems by exploiting the application behavior. There is a need for an automatic generation of hardware to determine the required silicon area, clock frequency, and power consumption of the candidate architectures. In this paper, we present a language based exploration framework that automatically generates synthesizable RTL models for pipelined processors. Our framework allows varied micro-architectural modifications, such as, addition of pipeline stages, pipeline paths, opcodes and new functional units. The generated RTL is synthesized to determine the area, power, and clock frequency of the modified architectures. Our exploration results demonstrate the power of reuse in composing heterogeneous architectures using functional abstraction primitives allowing for a reduction in the time for specification and exploration by at least an order of magnitude.

关键词： Power generation Clocks Pipelines Embedded software software performance software tools Distributed power generation Embedded system Application software hardware

来源：评论

学校读者我要写书评

暂无评论

Experiences teaching synthesis of FPGAs and testable ASICS

Experiences teaching synthesis of FPGAs and testable ASICS

引用

IEEE international conference on Microelectronic systems Education

作者： D.W. Bouldin Electrical Engineering University of Tennessee Knoxville TN USA

Microelectronic system designers are increasingly capturing their designs using hardware description languages such as VHDL and Verilog. The designs are then most often synthesized into programmable logic devices such as field-programmable gate arrays (FPGAs). This approach places the emphasis on a high-level design which reduces time to market by relying on synthesis software and programmable logic to produce working prototypes rapidly. These prototypes may then be altered as requirements change or convert into high-volume mask gate arrays or other application-specific integrated circuits (ASICs) when the demand is known to be sufficient. These ASICs, however, must be designed to be testable to screen out those with manufacturing defects. Hence, scan logic must be inserted, test vectors generated and fault grading performed to ensure a high level of testability. Experiences encountered from teaching a two-semester graduate sequence on these topics are summarized.

关键词： Education Field programmable gate arrays Application specific integrated circuits Programmable logic arrays Circuit testing Logic testing hardware design languages Programmable logic devices software prototyping Microelectronics

来源：评论

学校读者我要写书评

暂无评论

Applying formal methods for the design of wireless telecommunication systems 07

Applying formal methods for the design of wireless telecommu...

引用

proceedings of the 3rd international conference on Mobile multimedia communications

作者： Konstantinos Antonis Nikolaos S. Voros TEI of Lamia Lamia Greece TEI of Mesolonghi Ethniki Odos Antiriou Nafpaktou Varia Nafpaktos Greece

ISBN: (纸本)9789630626705

The increasing complexity of modern telecommunication systems is one of the main issues encountered in most telecom products. Despite the plethora of methods and tools for efficient system design, verification and validation phases are still consuming significant part of the overall design time. The proposed approach outlines the use of the B method/language for producing correct-by-construction implementations of telecommunication systems. The method described is supported by appropriate tools that automate the process of proving that system properties are maintained during the various design stages. The feasibility of the latter is evaluated in practice through the design of a real world telecom application, borrowed from the domain of wireless telecommunication networks.

关键词： wireless systems B language formal methods hardware/software codesign

来源：评论

学校读者我要写书评

暂无评论

proceedings 2003. Design Automation conference (IEEE Cat. No.03CH37451)

Proceedings 2003. Design Automation Conference (IEEE Cat. No...

引用

Design Automation conference

The following topics are dealt with: real challenges and solutions for validating system-on-Chip, reshaping EDA for power, design for manufacturability and global routing, design analysis techniques, embedded hardware design case studies, emerging design and tool challenges in RF and wireless applications, power grid analysis and optimization, low-power embedded system design, cyclic and non-cyclic combinational synthesis, managing leakage power, timing-oriented placement, issues in partitioning and design space exploration for codesign, nanotechnology: design implications and CAD challenges, simulation coverage and generation for verification, tool support for architectural decisions in embedded systems, new topics in logic synthesis, coping with variability: the end of deterministic design, testbench, verification and debugging: practical considerations, delay and noise modeling in the nanometer regime, modeling issues in the design of embedded systems, how application/technology evolutions will shape classical EDA, SAT and BDD algorithms for verification tools, elements of functional and performance analysis, nonlinear model order reduction, novel techniques in high-level synthesis, mixed-signal design and simulation, novel self-test methods, technology mapping, buffering, and bus design, compilation techniques for reconfigurable devices, architectural power estimation and optimization, techniques for reconfigurable logic applications, test and diagnosis for complex designs, highlights of ISSCC: high-speed heterogenous design techniques, highlights of ISSCC and the design of state-of-the-art microprocessors, high frequency interconnect modeling, novel approaches in test cost reduction, retargetable tools for embedded software, ASIC design in nanometer era - dead or alive?, floorplanning and placement, advances in SAT, novel design methodologies and signal integrity, memory optimization for embedded systems, design automation for quantum circuits, energy-aware sys

关键词： Integrated circuit design Design automation

来源：评论

学校读者我要写书评

暂无评论

Alis: a light-weight logic synthesis for digital signal processing of audio visual

Alis: a light-weight logic synthesis for digital signal proc...

引用

IEEE international conference on Verilog HDL

作者： T. Yatani K. Sato M. Niizato Semicond. Co. Sony Corp. Atsugi Japan Research Center Sony Corporation Tokyo Japan Sony Corporation Atsugi Japan

We have developed a high-speed, light-weight logic synthesis system, called Alis, with a high-level library of mathematical operation circuits for signal processing. Instead of minimizing circuit logic, we have concentrated on synthesizing better operation circuits using optimal cells of the target ASIC library because most of digital AV signal processing circuits are mathematical operation circuits. As a result, our system can synthesize circuits at least 10 times faster than conventional commercial synthesis systems.

关键词： Signal synthesis Digital signal processing hardware design languages Logic circuits Application specific integrated circuits Signal processing Synthesizers software libraries Circuit synthesis Logic design

来源：评论

学校读者我要写书评

暂无评论

hardware supported adaptive data collection for networks on chip

Hardware supported adaptive data collection for networks on ...

引用

2013 IEEE 37th Annual Computer software and Applications conference, COMPSAC 2013

作者： Heisswolf, Jan Weichslgartner, Andreas Zaib, Aurang Konig, Ralf Wild, Thomas Herkersdorf, Andreas Teich, Jurgen Becker, Jurgen Karlsruhe Institute of Technology Germany University of Erlangen Nuremberg Germany Technical University Munich Germany

ISBN: (纸本)9780769549798

Managing future many-core architectures with hundreds of cores, running multiple applications in parallel, is very challenging. One of the major reasons is the communication overhead required to handle such a large system. Distributed management is proposed to reduce this overhead. The architecture is divided into regions which are managed separately. The instance managing the region and the applications running within the regions need to collect data for various reasons from time to time, e.g., to collect data for proper mapping decision, to synchronize tasks or to aggregate computation results. In this work, we propose and investigate different strategies for adaptive data collection in meshed Networks on Chip. The mechanisms can be used to collect data within regions, which are defined during run-time in respect of size and position. The mechanisms are investigated while considering delay, NoC utilization and implementation costs. The results show that the selection of the used mechanism depends on the requirements. synthesis results compare area overhead, timing impact and energy consumption. © 2013 IEEE.

关键词： Network-on-chip

来源：评论

学校读者我要写书评

暂无评论

Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors 08

Yield maximization for system-level task assignment and conf...

引用

proceedings of the 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Love Singhal Sejong Oh Eli Bozorgzadeh University of California Irvine Irvine CA USA Korea Advanced Institute of Science and Technology Daejeon South Korea

ISBN: (纸本)9781605584706

Configurable multiprocessor system is a promising design alternative because of its high degree of flexibility, short development time, and potentially high performance under constraints and challenges driven by applications. An important design challenge at 45nm for multi-core system is manufacturing process variation. Due to increasing concern of WID variation, designers will have to choose configurations of processing cores that maximize yield of the system while not affecting performance and throughput constraints. Due to interdependency between processor configuration selection and task allocation and its impact on yield and latency constraints, we tackle both problems simultaneously. In this paper, we propose the problem of task allocation and configuration selection for yield optimization. We prove the problem is NP-hard and propose an optimal pseudo-polynomial on Serial-Parallel graphs. We target streaming applications in pipelined reconfigurable multiprocessor systems. We provide a case study of configurable Leon processors as the cores implemented on FPGA. Results show that proposed problem could result in significant improvement of the timing yield of the system by exploiting extra slack on tasks.

关键词： configuration selection process variation delay budgeting within-die variation task allocation timing yield

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共156页 << < 140 141 142 143 144 145 146 147 148 149 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：