Latency tolerance is one of main problems of softwaresynthesis in the design of hardware-software mixed systems. This paper presents a methodology for speeding up systems through latency tolerance which is obtained b...
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ISBN:
(纸本)0818675977
Latency tolerance is one of main problems of softwaresynthesis in the design of hardware-software mixed systems. This paper presents a methodology for speeding up systems through latency tolerance which is obtained by decomposition of tasks and generation of an efficient scheduler. The task decomposition process focuses on the dependency analysis of system i/o operations. Scheduling of the decomposed tasks is performed in a mixed static and dynamic fashion. Experimental results show the significance of our approach.
This paper presents a hardware-software (HW-SW) partitioning algorithm to be used in HW-SW codesign of an embedded real-time system. The algorithm interacts with the period calibration method such that the period assi...
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This paper presents a hardware-software (HW-SW) partitioning algorithm to be used in HW-SW codesign of an embedded real-time system. The algorithm interacts with the period calibration method such that the period assignment and HW-SW partitioning of real-time tasks are considered in a single framework. The partitioning algorithm makes use of three heuristics and one random transformation rule in order to quickly find a feasible HW-SW partition which most likely leads to the minimum HW cost design. As an experimental study, two partitioning algorithms, one that is based on the proposed heuristics and the other based on simulated annealing have been implemented. We have performed preliminary experiments and present the result.
The model refinement task in system-level synthesis transforms a specification from a functional model to a chosen implementation model. In this paper, we categorize several commonly-used implementation models and the...
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ISBN:
(纸本)9780818674235
The model refinement task in system-level synthesis transforms a specification from a functional model to a chosen implementation model. In this paper, we categorize several commonly-used implementation models and then describe a set of refinement procedures to transform a specification to each of these implementation models. We also present a set of experimental results to compare the implementation models and to demonstrate how the proposed approach is used to explore different implementation styles.
We present experiences with the hardware/software co-design of a high-performance video board using co-synthesis and high-level synthesis tools. Consisting of a multiprocessor DSP, a coprocessor, 4 local memory banks ...
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We present experiences with the hardware/software co-design of a high-performance video board using co-synthesis and high-level synthesis tools. Consisting of a multiprocessor DSP, a coprocessor, 4 local memory banks and interface and switching circuits, the board executes one of two professional studio algorithms with very different characteristics. This board could replace a much larger system currently in use. While the CAD tools allowed for a widely automated what-if analysis and were also used for most of the final design. The design process also highlighted some missing links in an optimizing co-design of high-performance systems. These missing links still prevent an efficient hardware/software optimization process. Flexibility requirements played an important role in the design process and had a massive impact on the target architecture, the hardware/software distribution, and the tool application.
We describe a framework that constructs interfaces between simulation tools and real-time prototyping hardware in a high-level DSP synthesis environment. A goal of this work is to abstract the concept of the interface...
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We describe a framework that constructs interfaces between simulation tools and real-time prototyping hardware in a high-level DSP synthesis environment. A goal of this work is to abstract the concept of the interface so that customized links are not required between each simulation and hardware engine. To support a new engine, the DSP system designer must define two pairs of communication primitives between the new tool and host workstation. The interface construction mechanism provides incremental compilation of subsystems in a system specification into the high-level DSP synthesis environment. We illustrate this framework with practical examples that have been constructed in Ptolemy.
The proceedings contain 29 papers. The special focus in this conference is on Application and Theory of Petri Nets. The topics include: Actors, nets, and the problem of abstraction and composition;temporal uncertainty...
ISBN:
(纸本)3540613633
The proceedings contain 29 papers. The special focus in this conference is on Application and Theory of Petri Nets. The topics include: Actors, nets, and the problem of abstraction and composition;temporal uncertainty and fuzzy-timing high-level petri nets;compositionality in state space verification methods;on liveness and controled siphons in petri nets;behavioral and structural composition rules preserving liveness by synchronization for colored FIFO nets;high level synthesis of synchronous parallel controlers;non sequential semantics for contextual P/T nets;integrating hardware and software models;designing and verifying a communications gateway using colored petri nets and design/CPN;expected impulse rewards in markov regenerative stochastic petri nets;asynchronous composition of high level petri nets;a formal definition of hierarchical predicate transition nets;reduced state space representation for unbounded vector state spaces;modeling and analysis of distributed program execution in BETA using colored petri nets;reachability analysis based on structured representations;the SEA language for system engineering and animation;a new iterative numerical solution algorithm for a class of stochastic petri nets;a structural approach for the analysis of petri nets by reduced unfoldings;the consistent use of names and polymorphism in the definition of object petri nets;designing a security system by means of colored petri nets;modeling and analysing DART systems through high-level petri nets;behavioral equivalence for infinite systems;topological aspects of traces and asynchronous control device design by net model behavior simulation.
Different ways of implementing and designing arithmetic functions for 16/32 bit integers in FPGA technology are studied. A comparison of four different design methods is also included. The results are used to increase...
Different ways of implementing and designing arithmetic functions for 16/32 bit integers in FPGA technology are studied. A comparison of four different design methods is also included. The results are used to increase the overall system performance in a dedicated 3D image analysis prototype system by moving a vector length calculation from software to hardware. The conclusion is that by adding one relatively simple board containing two FPGAs in the prototype setup, the total computing time is reduced by 30%. The total amount of image data, in this case 300 Mbyte, which has to be transmitted via the network is reduced by a factor of two, and the required network bandwidth is reduced similarly.
The rough controller is a processor of decision tables whose design is motivated by rough set theory. The paper briefly presents our implementation of the rough controller and formulates a methodology of rough control...
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The rough controller is a processor of decision tables whose design is motivated by rough set theory. The paper briefly presents our implementation of the rough controller and formulates a methodology of rough control systemsynthesis. The methodology defines the steps of the synthesis process, from knowledge acquisition to verification to implementation.
Test hardware for a digital FM modulator has been built using a direct digital synthesiser with a variable bit output. Both hardware and software simulations of the test system have been used to show that a 10 bit out...
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Test hardware for a digital FM modulator has been built using a direct digital synthesiser with a variable bit output. Both hardware and software simulations of the test system have been used to show that a 10 bit output is sufficient to produce demodulated signals which have a signal to distortion ratio of more than 80 dB.
We propose a new method for generating BDDs from hardware algorithm descriptions written in a programming language. Our system can deal with control structures, such as conditional branches (if-then-else) and data dep...
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ISBN:
(纸本)0818675977
We propose a new method for generating BDDs from hardware algorithm descriptions written in a programming language. Our system can deal with control structures, such as conditional branches (if-then-else) and data dependent loops (while-end). Once BDDs are generated, we can immediately check the equivalence of two different algorithm descriptions just by comparing BDDs. This method can also be applied to verification between algorithm-level and gate-level designs. Another interesting application is to synthesize loop-free logic circuits from algorithm descriptions. We show the experimental results for some practical examples, such as Greatest Common Divisor (GCD) calculation. Although our method has a limitation in size of problems, it is very practical and useful for actual design verification.
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