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Synterface: Efficient Chip-to-World Interfacing for Flow-Based Microfluidic Biochips Using Pin-Count Minimization

ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 54-54页

作者： Sridhar, Aditya Ibrahim, Mohamed Chakrabarty, Krishnendu Duke Univ Dept Elect & Comp Engn 130 Hudson Hall Durham NC 27708 USA

Flow-based microfluidic biochips can be used to perform bioassays by manipulating a large number of on-chip valves. These biochips are increasingly used today for biomolecular recognition, single-cell screening, and point-of-care disease diagnostics, and design-automation solutions for flow-based microfluidics enable the mapping and optimization of bimolecular protocols and software-based valve control. However, a key problem that has not received adequate attention is chip-to-world interfacing, which requires the use of off-chip control equipment to provide control signals for the on-chip valves. This problem is exacerbated by the increase in the number of valves as chips get more complex. To address the interfacing problem, we present an efficient pin-count minimization (synthesis) problem, referred to as Synterface, which uses on-chip microfluidic logic gates and optimization based on concepts from linear algebra. We present results to show that Synterface significantly reduces pin-count and simplifies the external interface for flow-based microfluidics.

关键词： Microfluidic biochips chip-to-world interfacing synthesis logic gates

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The FASTER vision for designing dynamically reconfigurable systems

The FASTER vision for designing dynamically reconfigurable s...

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IEEE international conference on Integrated Circuit Design and Technology (ICICDT)

作者： M. D. Santambrogio C. Pilato D. Pnevmatikatos K. Papadimitriou D. Stroobandt D. Sciuto Dipartimento di Elettronica Informazione e Bioingegneria Politecnico di Milano Italy Foundation for Research and Technology-Hellas Greece Computer Systems Laboratory Ghent University Belgium

ISBN: (纸本)9781467347402

Extending product functionality and lifetime requires constant addition of new features to satisfy the growing customer needs and the evolving market and technology trends. software component adaptivity is straightforward but not enough: recent products include hardware accelerators for reasons of performance and power efficiency that also need to adapt to new requirements. Reconfigurable logic allows the definition of new functions to be implemented in dynamically instantiated hardware units, combining adaptivity with hardware speed and efficiency. For the Intrusion Detection system example, new rules can be hardcoded into the reconfigurable logic, achieving high performance, while providing the necessary adaptivity to new threats. The FASTER (Facilitating Analysis and synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform combining a general purpose processor with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design- and run-time, the capabilities of partial dynamic reconfiguration. The FASTER project will facilitate the use of reconfigurable hardware by providing a complete methodology that enables designers to easily implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology.

关键词： hardware Runtime Field programmable gate arrays software Parallel processing Schedules Acceleration

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Arbitrary function approximation in HDLs with application to the N-body problem

Arbitrary function approximation in HDLs with application to...

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IEEE international conference on Field-Programmable Technology (FPT)

作者： C.H. Ho K.H. Tsoi H.C. Yeung Y.M. Lam K.H. Lee P.H.W. Leong R. Ludewig P. Zipf A.G. Ortiz M. Glesner Department of Computer Science and Engineering The Chinese University of Hong Kong Shatin NT HK Institute of Microelectronic Systems Darmstadt University of Technology Germany

A module generator is described that allows for the generation of synthesizable VHDL modules which implement arbitrary functions in fixed point precision using the Symmetric Table Addition Method (STAM). This module generator was interfaced to a high level synthesis tool "fly" which automatically generates fully-pipelined circuits from a Perl-like language. The resulting system was applied to the N-body problem and results are presented. It was found that a function generator module is a very useful addition to a hardware description language.

关键词： Function approximation hardware design languages Field programmable gate arrays Application software High level synthesis software libraries Algorithm design and analysis Table lookup Computer science Microelectronics

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Special Session: Mitigating Side-channel Attacks through Circuit to Application Layer Approaches

Special Session: Mitigating Side-channel Attacks through Cir...

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proceedings of the 2023 international conference on hardware/software codesign and system synthesis

作者： Nima Kavand Armin Darjani Jens Trommer Giulio Galderisi Thomas Mikolajick Nicolai Mueller Amir Moradi Chongzhou Fang Ning Miao Han Wang Sai Manoj Pudukotai Dinakarrao Houman Homayoun Benjamin Hettwer Luca Parrini Akash Kumar TU Dresden Dresden Saxony Germany Namlab gGmbH Dresden Saxony Germany Ruhr University Bochum Bochum North Rhine-Westphalia Germany UC Davis Davis California USA Temple University Philadelphia Pennsylvania USA George Mason University Fairfax Virginia USA Robert Bosch GmbH Renningen Baden-wuerttemberg Germany

ISBN: (纸本)9798400702891

Side-Channel Attacks (SCAs), which are always considered a severe threat to the security of the cryptographic circuits, today can also be employed to extract IP secrets and neural network models. Hence, developing novel security solutions at different design levels is crucial. In this paper, we explore recent countermeasures at the circuit, algorithmic, and microarchitecture levels. First, we explain how Reconfigurable Field-Effect Transistor (RFET), as a beyond CMOS technology, enables us to provide both IP and data protection against SCAs at the circuit level. Second, we investigate an automated method for generating masked circuits as an algorithmic solution, and then we review machine learning-based SCA detection mechanisms at the microarchitecture level. Finally, we discuss emerging threats of SCAs from the industrial point of view.

关键词： hardware security side-channel analysis emerging technology masking

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CODEF: a system level design space exploration tool

CODEF: a system level design space exploration tool

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international conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： M. Auguin L. Capella F. Cuesta E. Gresset Laboratoire I3S Université de Nice Sophia Antipolis France Philips Semiconductors La Valbonne France

The increasing complexity of embedded applications combined with the advances in chip integration make the design process a very challenging task. Due to this rising complexity, the design under performance, area and consumption constraints of a system-on-a-chip (SOC) composed of mixed software-hardware units, becomes increasingly intricate. This paper presents a method and an associated tool (CODEF) which allow the designer to do an automatic and/or interactive system design space exploration in order to construct cost effective embedded real-time architectures dedicated to complex signal processing applications. The method is based on a recursive partitioning algorithm followed by a communication synthesis procedure.

关键词： system-level design Space exploration Application software system-on-a-chip Signal design Signal processing algorithms Process design Interactive systems Costs Real time systems

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Cache Locking Content Selection Algorithms for ARINC-653 Compliant RTOS

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 76-76页

作者： Dugo, Alexy Torres Aurora Lefoul, Jean-Baptiste De Magalhaes, Felipe Gohring Assal, Dahman Nicolescu, Gabriela Ecole Polytech Montreal 2900 Boul Edouard Montpetit Montreal PQ Canada Mannarino Syst & Software Inc Montreal PQ Canada

Avionic software is the subject of stringent real time, determinism and safety constraints. software designers face several challenges, one of them being the interferences that appear in common situations, such as resource sharing. The interferences introduce non-determinism and delays in execution time. One of the main interference prone resources are cache memories. In single-core processors, caches comprise multiple private levels. This breaks the isolation principle imposed by avionic standards, such as the ARINC-653. This standard defines partitioned architectures where one partition should never directly interfere with another one. In cache-based architectures, one partition can modify the cache content of another partition. In this paper, we propose a method based on cache locking to reduce the non-determinism and the contention on lower level memories while improving the time performances.

关键词： Critical systems ARINC-653 interference cache locking aerospace

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Transformational partitioning for co-design of multiprocessor systems 97

Transformational partitioning for co-design of multiprocesso...

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proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

作者： Gilberto Fernandes Marchioro Jean-Marc Daveau Ahmed Amine Jerraya System-Level Synthesis Group TIMA/INPG - Grenoble France

ISBN: (纸本)9780818682001

This paper presents the underlying methodology of Cosmos, an interactive approach for hardware/software co-design capable of handling multiprocessor systems and distributed architectures. The approach covers the co-design process through a set of user guided transformations allowing semi-automatic partitioning. The transformations are based on a powerful set of primitives for functional partitioning, structural reorganization and communication transformation. It leads to a fast transformation of a system-level specification into an architecture with a short design time and fast exploration of design space. The application of this approach is illustrated using several design examples starting from a system-level specification given in SDL to a distributed hardware/software architecture described in C/VHDL. We show that the use of transformational approach allows: Application of the expertise of the designer during partitioning ; - the user to understand the results of the co-design process ; the process to take into account partial existing solutions ; - large design space exploration ; the designer to start from a very high-level specification language of the system to be designed.

关键词： hardware/software co-design

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A flow-based network monitoring system used for CSCW in design

A flow-based network monitoring system used for CSCW in desi...

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international conference on Computer Supported Cooperative Work in Design

作者： Bo Yang Yi Li Yuehui Chen Runzhang Yuan State Key Laboratory of Advanced Technology for Materials Synthesis and Processing Wuhan University of Science and Engineering China School of Information Science and Technology Jinan University China

ISBN: (纸本)184000025

Technology trends in today's cooperative design environments are making it more and more important to monitor the network performance and ensure the network security. This paper describes the design and implementation of a distributed network traffic monitoring system based on embedded NetFlow hardware and software engines. The system architecture and design principles were introduced in the paper, some discussions were also presented about the NetFlow-based network monitoring technologies. The system had been successfully used to monitor highspeed campus networks at full wire speed without packet sampling in scenarios where commercial NetFlow collectors could not be used due to their limitations. Results show that this is an effective mechanism to identify, diagnose, and determine controls for network activities in CSCW environments and other network-based applications.

关键词： Monitoring Intelligent networks Telecommunication traffic Switches Materials science and technology Sampling methods Probes Protocols Network synthesis Information science

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Modular robotics: design and examples

Modular robotics: design and examples

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international conference on Emerging Technologies and Factory Automation (ETFA)

作者： A.C. Sanderson Center for Advanced Technology in Robotics and Automation and Department of Electrical Computer and Systems Engineering Rensselaer Polytechnic Institute RPI Troy NY USA Intellignet robotics Laboratory Institute for Information Science and Electronics University of Tsukuba Tsukuba Japan

An object-oriented modular approach to the engineering of complex robotic systems emphasizes reliability, reusability, ease of development, and user and network interfaces. This modular approach integrates many architectural principles and computational techniques which support adaptive and learning capability at the local, modular level. The TETROBOT is a modular and reconfigurable robotic system which was developed to demonstrate the reliable performance in a wide variety of task domains through reconfiguration of the same fundamental hardware and software components. Such a modular approach emphasizes the synthesis and integration of engineering modules and takes advantage of object-oriented engineering principles to design for a family of tasks. This paper provides an overview of the TETROBOT modular system and describes three modular systems in other applications domains.

关键词： Robots hardware Robustness Humans Indium phosphide Utility programs

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Designing an online and real time simulation, control and monitoring of disturbances in an intelligent manufacturing system

Designing an online and real time simulation, control and mo...

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IEEE international conference on Industrial Informatics (INDIN)

作者： M.N. Yuniarto A.W. Labib Manufacturing Division Department of Mechanical Aerospace and Manufacturing Engineering University of Manchester Institute of Science and Technology Manchester UK

We propose the principles and methodologies for developing an online and real-time simulation system for controlling and monitoring an intelligent manufacturing system. An online and real-time system is a system that always been dynamically connected to another system so if there is a changing in state within one system, the other system will be affected directly. The research focuses on the application of these principles and methodologies into a manufacturing system model that is developed. The combination of the two features (online and real time) and the possibility to add an intelligent feature (by using knowledge-based approach) into the online and real time system will lead to an improvement of manufacturing system performance, which will be more reactive, responsive, flexible and also saving time for making decisions if there are any changing or disturbances in the manufacturing system. In short this paper is mainly concerned with controlling and monitoring disturbance that is caused by deterioration in state, for example machine/resource breakdown. We aim at addressing two fundamental issues. The first issue is related to the existence of a gap between shop floor level systems in the form of programmable logic controllers (PLCs) and sensor at one level and scheduling databases such as material requisition planning (MRPII), enterprise resource planning (ERP) and simulation at the supervisory/managerial level. The second issue is related to the parallel interface of maintenance data collection and decision support with the production system. The development of hardware and software is presented to address the two issues. The hardware is a miniaturised/model of a manufacturing system that is controlled by a PLC, a supervisory control and data acquisition (SCADA) systems and a PC in real-time manner. The software is developed and used to monitor and control the miniaturised system in online and real-time condition.

关键词： Real time systems Intelligent manufacturing systems Manufacturing systems Programmable control Enterprise resource planning SCADA systems Control system synthesis Condition monitoring hardware Electric breakdown

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