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international conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： P. Duncan S. Swamy S. Sprouse D. Potasz R. Jain N. Gafter W. Cammack Y. Wong W. Gass UCLA Los Angeles CA USA Texas Instruments Inc. Dallas TX USA

Hi-PASS, a CAD system for digital signal processor (DSP) architecture synthesis, has been developed to automatically produce maximally parallel VLSI designs for real-time applications. The target DSP applications are the class for which desired sample rates are so high that time sharing of hardware is not feasible. Hi-PASS accepts a C code description of the design to be synthesized and produces a structural description of the final design which can be fabricated using standard cells provided by the Lager IV silicon assembly system. Hi-PASS is a collection of modular tools, several of which contain new techniques within the field of synthesis. C code is converted into a flowgraph using a technique known as symbolic interpretation, including new methods for handling certain types of input-dependent control flow. The HOPS program is a heuristic search flowgraph optimizer tailored for the arithmetic intensive structures necessary for real-time DSP applications. The high throughput rates necessary for these applications also require that retiming be used to provide very short inter-register delay times. A new retiming tool has been developed which allows for computationally efficient bit-level retiming.< >

关键词： Concurrent computing Digital signal processing Signal synthesis Application software Design automation Digital signal processors Very large scale integration Signal design Real time systems Time sharing computer systems

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Polar: Function Code Aware Fuzz Testing of ICS Protocol

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 93-93页

作者： Luo, Zhengxiong Zuo, Feilong Jiang, Yu Gao, Jian Jiao, Xun Sun, Jiaguang Tsinghua Univ Sch Software BNRist KLISS Beijing Peoples R China Villanova Univ Dept Comp Sci & Engn Villanova PA 19085 USA

Industrial Control system (ICS) protocols are widely used to build communications among system components. Compared with common internet protocols, ICS protocols have more control over remote devices by carrying a specific field called "function code", which assigns what the receive end should do. Therefore, it is of vital importance to ensure their correctness. However, traditional vulnerability detection techniques such as fuzz testing are challenged by the increasing complexity of these diverse ICS protocols. In this paper, we present a function code aware fuzzing framework - Polar, which automatically extracts semantic information from the ICS protocol and utilizes this information to accelerate security vulnerability detection. Based on static analysis and dynamic taint analysis, Polar initiates the values of the function code field and identifies some vulnerable operations. Then, novel semantic aware mutation and selection strategies are designed to optimize the fuzzing procedure. For evaluation, we implement Polar on top of two popular fuzzers - AFL and AFLFast, and conduct experiments on several widely used ICS protocols such as Modbus, IEC104, and IEC 61850. Results show that, compared with AFL and AFLFast, Polar achieves the same code coverage and bug detection numbers at the speed of 1.5X-12X. It also gains increase with 0%-91% more paths within 24 hours. Furthermore, Polar has exposed 10 previously unknown vulnerabilities in those protocols, 6 of which have been assigned unique CVE identifiers in the US National Vulnerability Database.

关键词： Fuzz testing industrial control system protocol function code vulnerability detection

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COMET: Communication-optimised multi-threaded error-detection technique

COMET: Communication-optimised multi-threaded error-detectio...

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proceedings of the international conference on Compilers, Architectures and synthesis for Embedded systems (CASES)

作者： Konstantina Mitropoulou Vasileios Porpodas Timothy M. Jones Computer Laboratory University of Cambridge UK Intel USA

ISBN: (纸本)9781509035892

Relentless technology scaling has made transistors more vulnerable to soft, or transient, errors. To keep systems robust against these, current error detection techniques use different types of redundancy at the hardware or the software level. A consequence of these additional protection mechanisms is that these systems tend to become slower. In particular, software error-detection techniques degrade performance considerably, limiting their uptake. This paper focuses on software redundant multi-threading error detection, a compiler-based technique that makes use of redundant cores within a multi-core system to perform error checking. Implementations of this scheme feature two threads that execute almost the same code: the main thread runs the original code and the checker thread executes code to verify the correctness of the original. The main thread communicates the values that require checking to the checker thread to use in its comparisons. We identify a major performance bottleneck in existing schemes: poorly performing inter-core communication and the generated code associated with it. Our study shows this is a major performance impediment within existing techniques since the two threads require extremely fine-grained communication, on the order of every few instructions. We alleviate this bottleneck with a series of code generation optimisations at the compiler level. We propose COMET (Communication-Optimised Multi-threaded Error-detection Technique), which improves performance across the NAS parallel benchmarks by 31.4% (on average) compared to the state-of-the-art, without affecting fault-coverage.

关键词： Instruction sets Optimization Synchronization Transient analysis hardware Transistors

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Modeling and Analysis of Windowed Synchronous Algorithms

Modeling and Analysis of Windowed Synchronous Algorithms

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international conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： J. Keinert C. Haubelt J. Teich Institute for Integrated Circuits IIS Fraunhofer Erlangen Germany Hardware-Software-Co-Design Department of Computer Science 12 University of Erlangen Nuremberg Germany

Sliding window algorithms are fundamental parts of each image processing system. Especially those belonging to the class of static algorithms offer various possibilities for analysis and optimization. Only if this potential is exploited, a high level synthesis of such algorithms will lead to efficient implementations. Such an analysis relies on an efficient representation by a well-defined model of computation. It must abstract important properties of sliding windows as for instance the relation between input and output data as well as the required buffer space. In this paper, a corresponding static model of computation for sliding window algorithms is elaborated, called windowed synchronous data flow (WSDF). Its main focus lies on applications with two or more dimensions. Furthermore, the WSDF balance equation is derived allowing to verify bounded token accumulation during execution

关键词： Algorithm design and analysis Signal processing algorithms Computational modeling Processor scheduling Equations Buffer storage Image processing Data flow computing Multidimensional systems Computer science

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The microelectronic device selection process

The microelectronic device selection process

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Annual IEEE international conference and Exhibit ASIC

作者： F. Blitzer J.R. Samson Honeywell Inc. FL USA

A methodology which has yielded excellent results in identifying critical device needs for complex military systems is described. This methodology is illustrated using examples derived from advanced satellite and other processing system studies. The microelectronic device selection process begins with the identification of mission requirements. The system designer then identifies the system functions necessary to perform the mission and allocates these functions to architectural elements within the system. At some level in this allocation is the processing system (hardware and software). From this point, the synthesis of possible processing concepts and configurations is initiated. This iterative process includes functional, technology, and packaging trade studies which establish the parameters of the trade space(s) involved and identify design sensitivities. From these analyses, the designer and his customer identify tradeoff criteria so that the lower level trades can be made to isolate technology needs. These needs may be satisfied with mature technology or, if schedule permits, the development of new or maturing technology. The key elements of this selection process are technology and risk assessment. Particular emphasis is placed on these two aspects of the process.< >

关键词： Microelectronics Space technology Isolation technology Satellites Risk management Electronic switching systems hardware Integrated circuit technology Process design Application specific integrated circuits

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A methodology for rapid analysis and optimization of embedded systems

A methodology for rapid analysis and optimization of embedde...

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international conference and Workshop on Engineering of Computer-Based systems

作者： H.-J. Eikerling W. Hardt J. Gerlach W. Rosenstiel Technische Informatik Universitat Tubingen Tubingen Germany Mathematik-Informatik Universitat Paderborn Paderborn Germany

The paper describes an environment for the rapid analysis, synthesis and optimization of embedded systems. Since the implementation of these systems is rather complicated, we propose a methodology which automates the entire design flow. Flexibility is achieved by allowing manual intervention which is realized via a modular implementation of algorithms which are being provided. The applicability of the proposed approach is shown in terms of an example (UNIX command grep).

关键词： Optimization methods Embedded system hardware Computer architecture Assembly systems Time to market software design Constraint optimization Design optimization Humans

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Statistical Verification of Hyperproperties for Cyber-Physical systems

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 92-92页

作者： Wang, Yu Zarei, Mojtaba Bonakdarpour, Borzoo Pajic, Miroslav Duke Univ 100 Sci DrHudson Hall Rm 220 Durham NC 27708 USA Iowa State Univ 207 Atanasoff Hall Ames IA 50011 USA

Many important properties of cyber-physical systems (CPS) are defined upon the relationship between multiple executions simultaneously in continuous time. Examples include probabilistic fairness and sensitivity to modeling errors (i.e., parameters changes) for real-valued signals. These requirements can only be specified by hyperproperties. In this article, we focus on verifying probabilistic hyperproperties for CPS. To cover a wide range of modeling formalisms, we first propose a general model of probabilistic uncertain systems (PUSs) that unify commonly studied CPS models such as continuous-time Markov chains (CTMCs) and probabilistically parametrized Hybrid I/O Automata (P(2)HIOA). To formally specify hyperproperties, we propose a new temporal logic, hyper probabilistic signal temporal logic (HyperPSTL) that serves as a hyper and probabilistic version of the conventional signal temporal logic (STL). Considering the complexity of real-world systems that can be captured as PUSs, we adopt a statistical model checking (SMC) approach for their verification. We develop a new SMC technique based on the direct computation of significance levels of statistical assertions for HyperPSTL specifications, which requires no a priori knowledge on the indifference margin. Then, we introduce SMC algorithms for HyperPSTL specifications on the joint probabilistic distribution of multiple paths, as well as specifications with nested probabilistic operators quantifying different paths, which cannot be handled by existing SMC algorithms. Finally, we show the effectiveness of our SMC algorithms on CPS benchmarks with varying levels of complexity, including the Toyota Powertrain Control system.

关键词： Cyber-physical systems hyperproperties statistical model checking embedded control software

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High-Level synthesis of Approximate Designs under Real-Time Constraints

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 59-59页

作者： Leipnitz, Marcos T. Nazar, Gabriel L. Univ Fed Rio Grande do Sul Informat Inst Av Bento Goncalves 9500 BR-91501970 Porto Alegre RS Brazil

The adoption of High-Level synthesis (HLS) has increased as the latest HLS tools have evolved to provide high-quality results while improving productivity and time-to-market. Concurrently, many works have been proposing the incorporation of approximate computing techniques within HLS toolchains, allowing automated generation of inexact circuits for error-tolerant application domains with the aim of trading-off computation accuracy with area/power savings or performance improvements. Thus, when attempting to make a design meet timing requirements, designers of real-time systems using HLS may resort to approximation approaches. However, current approximate HLS tools do not allow specifying real-time constraints, being instead error-constrained to explore area, power, or performance optimizations. In this work, we propose an approximate HLS framework for real-time systems that can be integrated with state-of-the-art HLS tools. With this framework designers can specify real-time constraints and satisfy them while minimizing the output error. It uses scheduling information and Worst-Case Execution Time (WCET) analysis for iteratively exploring time-error trade-offs of approximations in the time-critical execution path. Experimental results on signal and image processing benchmarks show that we can reduce the WCET of exact designs by up to 35% with acceptable quality degradation.

关键词： High-level synthesis approximate computing worst-case execution time design space exploration

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Robust Controller Design and Mechaneza Tion for Precision Platform Alignment of the Trident II Inertial Measurement Unit (IMU)

Robust Controller Design and Mechaneza Tion for Precision Pl...

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IEEE Regional conference on Aerospace Control systems

作者： D.A. Hill J.R. Strunk B.J. Purslow R.W. Bass AUTONETICS Strategic Systems Division Electronics Design Group Rockwell International Anaheim CA USA Control and Signal Processing Department Rockwell International SCIENCE CENTER Thousand Oaks CA USA

This paper presents robust controller design and mechanization for precision alignment of the ESGN platform IMU of the Trident II navigation system. The primary design and mechanization tool is Integrated systems Inc. software MATRIXx, utilizing the Robust Control Module, and implementation using the AC-100 Rapid Prototyping system. In addition, alternative robust control algorithms are developed using both the Rockwell Science Center developed Rho-synthesis and The Mathworks Robust Control Toolbox with MATLAB. The design requires precision platform alignment to the gyro inertial reference with tracking errors less than one arcsecond in the presence of torque disturbances and sensor noise. Performance and stability robustness are required in the design to counteract large parameter variations that may occur in the actuator or in the the gimbal bearing friction. Figure 1 shows the stable platform (innermost gimbal) with the additional outer gimbals required for alignment about all three stable platform fixed axes. At present the development is focused upon implementing the prototyping hardware and controller for a single platform axis. The control designs presented here are H and Hinf robust control algorithms for Single Input Single Output (SIS0) control about the platform +z axis.

关键词： Robust control Prototypes hardware Control systems Signal processing algorithms MATLAB Acceleration Navigation Torque Robust stability

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Dynamic configuration of dataflow graph topology for DSP system design [video encoder example]

Dynamic configuration of dataflow graph topology for DSP sys...

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international conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Dong-Ik Ko S.S. Bhattacharyya Department of Electrical and Computer Engineering and Institute for Advanced Computer Studies University of Maryland College Park USA

Dataflow is widely used for designing DSP applications. Despite its intrinsic advantages, one weak point is its difficulty in flexible expression of applications with data dependent change in execution structure. This paper suggests an approach to providing dynamically configured dataflow graph topologies using a new modeling and synthesis technique called DGT (dynamic graph topology). DGT builds on PSDF semantics (B. Bhattacharya et al, IEEE Tran. on Sig. Proc., vol.49(10), p.2408-2421, 2001). All possible graph topologies for a given graph are obtained at compile time and the corresponding graph based on parameters and data is dynamically set up in an efficient manner at runtime before the invocation of the associated graph. systematic methods for reducing code and buffer size are applied based on characteristics of each configured graph. We have compared DGT against conventional modeling approaches through a detailed case study of an MPEG 2 video encoder system, and our experiments demonstrate the efficiency of the DGT approach.

关键词： Topology Digital signal processing Application software Runtime Data structures Boolean functions hardware Educational institutions Upper bound Equations

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