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MARS: mm Wave-based Assistive Rehabilitation system for Smart Healthcare

ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2021年第5期20卷 72-72页

作者： An, Sizhe Ogras, Umit Y. Univ Wisconsin Dept Elect & Comp Engn Madison WI 53706 USA

Rehabilitation is a crucial process for patients suffering from motor disorders. The current practice is performing rehabilitation exercises under clinical expert supervision. New approaches are needed to allow patients to perform prescribed exercises at their homes and alleviate commuting requirements, expert shortages, and healthcare costs. Human joint estimation is a substantial component of these programs since it offers valuable visualization and feedback based on body movements. Camera-based systems have been popular for capturing joint motion. However, they have high-cost, raise serious privacy concerns, and require strict lighting and placement settings. We propose a millimeter-wave (mmWave)-based assistive rehabilitation system (MARS) for motor disorders to address these challenges. MARS provides a low-cost solution with a competitive object localization and detection accuracy. It first maps the 5D time-series point cloud from mmWave to a lower dimension. Then, it uses a convolution neural network (CNN) to estimate the accurate location of human joints. MARS can reconstruct 19 human joints and their skeleton from the point cloud generated by mmWave radar. We evaluate MARS using ten specific rehabilitation movements performed by four human subjects involving all body parts and obtain an average mean absolute error of 5.87 cm for all joint positions. To the best of our knowledge, this is the first rehabilitation movements dataset using mmWave point cloud. MARS is evaluated on the Nvidia Jetson Xavier-NX board. Model inference takes only 64 mu s and consumes 442 mu J energy. These results demonstrate the practicality of MARS on low-power edge devices.

关键词： Human pose estimation point cloud millimeter wave smart healthcare

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Synterface: Efficient Chip-to-World Interfacing for Flow-Based Microfluidic Biochips Using Pin-Count Minimization

Synterface: Efficient Chip-to-World Interfacing for Flow-Bas...

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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Sridhar, Aditya Ibrahim, Mohamed Chakrabarty, Krishnendu Duke Univ Dept Elect & Comp Engn 130 Hudson Hall Durham NC 27708 USA

Flow-based microfluidic biochips can be used to perform bioassays by manipulating a large number of on-chip valves. These biochips are increasingly used today for biomolecular recognition, single-cell screening, and point-of-care disease diagnostics, and design-automation solutions for flow-based microfluidics enable the mapping and optimization of bimolecular protocols and software-based valve control. However, a key problem that has not received adequate attention is chip-to-world interfacing, which requires the use of off-chip control equipment to provide control signals for the on-chip valves. This problem is exacerbated by the increase in the number of valves as chips get more complex. To address the interfacing problem, we present an efficient pin-count minimization (synthesis) problem, referred to as Synterface, which uses on-chip microfluidic logic gates and optimization based on concepts from linear algebra. We present results to show that Synterface significantly reduces pin-count and simplifies the external interface for flow-based microfluidics.

关键词： Microfluidic biochips chip-to-world interfacing synthesis logic gates

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Cache Locking Content Selection Algorithms for ARINC-653 Compliant RTOS

Cache Locking Content Selection Algorithms for ARINC-653 Com...

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作者： Dugo, Alexy Torres Aurora Lefoul, Jean-Baptiste De Magalhaes, Felipe Gohring Assal, Dahman Nicolescu, Gabriela Ecole Polytech Montreal 2900 Boul Edouard Montpetit Montreal PQ Canada Mannarino Syst & Software Inc Montreal PQ Canada

Avionic software is the subject of stringent real time, determinism and safety constraints. software designers face several challenges, one of them being the interferences that appear in common situations, such as resource sharing. The interferences introduce non-determinism and delays in execution time. One of the main interference prone resources are cache memories. In single-core processors, caches comprise multiple private levels. This breaks the isolation principle imposed by avionic standards, such as the ARINC-653. This standard defines partitioned architectures where one partition should never directly interfere with another one. In cache-based architectures, one partition can modify the cache content of another partition. In this paper, we propose a method based on cache locking to reduce the non-determinism and the contention on lower level memories while improving the time performances.

关键词： Critical systems ARINC-653 interference cache locking aerospace

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hardware and software Co-Design for Object Detection with Modified ViBe Algorithm and Particle Filtering Based Object Tracking 14

Hardware and Software Co-Design for Object Detection with Mo...

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14th IEEE international conference on Industrial and Information systems, ICIIS 2019

作者： Wijesinghe, Yasitha M. Samarawickrama, Jayathu G. Dias, Dileeka University of Moratuwa Department of ENTC Katubedda Sri Lanka

ISBN: (纸本)9781728137063

This paper describes a hardware and software codesign approach for object detection and tracking algorithm which is based on modified ViBe background subtraction method and scale adaptable particle filtering algorithm. The modified ViBe performs with a close accuracy to the original work of ViBe but with less complexity and it outperforms the Mixture of Gaussian(MoG) method. Since the modified algorithm has a low off chip memory access requirement, the real time object detection in embedded level with the help of hardware acceleration techniques could be achieved. The implemented particle filtering algorithm is capable of adapting to the scale variation of the tracking objects. After careful investigation of the time consumption profile of each function in our algorithm, the complete algorithm was implemented in IoT edge devices targeted Avnet Ultra 96 development board which is based on Xilinx Zynq MPSoC. We could achieve an average frame rate of 40 fps for a 854× 480;resolution data set. © 2019 IEEE.

关键词： system-on-chip

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Work-in-Progress: Offloading Cache Configuration Prediction to an FPGA for hardware Speedup and Overhead Reduction

Work-in-Progress: Offloading Cache Configuration Prediction ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Ruben Vazquez Ann Gordon-Ross Greg Stitt University of Florida Gainesville United States

In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and hardware overhead reduction, while maintaining cache configuration predictions within 5% of th...

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Parametric Scheduler Characterization

Parametric Scheduler Characterization

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作者： Van Pinxten, Joost Geilen, Marc Basten, Twan Oce Technol BV POB 101 NL-5900 MA Venlo Netherlands Eindhoven Univ Technol Groene Loper 19Flux 4-132 NL-5612 AZ Eindhoven Netherlands TNO ESI Eindhoven Netherlands

Schedulers assign starting times to events in a system such that a set of constraints is met and system productivity is maximized. We characterize the scheduler behaviour for the case where decisions are made by comparing affine expressions of design parameters such as task workload, processing speed, robot travelling speed, or a controller's rise and settling time. Deterministic schedulers can be extended with symbolic execution, to keep track of the affine conditions on the parameters for which the scheduling decisions are made. We introduce a divide-and-conquer algorithm that uses this information to determine parameter regions for which the same sequence of decisions is taken given a particular scenario. The results provide designers insight in the impact of parameter changes on the performance of their system. The exploration can also be executed with the KLEE symbolic execution engine of the LLVM tool chain to extract the same results. We show that the divide-and-conquer approach provides the results much faster than the generic symbolic execution engine of KLEE. The results allow visualization of the sensitivity to all parameter combinations. The results of our approach therefore provide more insight in the sensitivity to parameters.

关键词： Real time scheduling system design re-entrant flexible manufacturing system

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An Ultra-Low Energy Human Activity Recognition Accelerator for Wearable Health Applications

An Ultra-Low Energy Human Activity Recognition Accelerator f...

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作者： Bhat, Ganapati Tuncel, Yigit An, Sizhe Lee, Hyung Gyu Ogras, Umit Y. Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA Daegu Univ Sch Comp & Commun Engn Daegu 38453 South Korea

Human activity recognition (HAR) has recently received significant attention due to its wide range of applications in health and activity monitoring. The nature of these applications requires mobile or wearable devices with limited battery capacity. User surveys show that charging requirement is one of the leading reasons for abandoning these devices. Hence, practical solutions must offer ultra-low power capabilities that enable operation on harvested energy. To address this need, we present the first fully integrated custom hardware accelerator (HAR engine) that consumes 22.4 mu J per operation using a commercial 65 nm technology. We present a complete solution that integrates all steps of HAR, i.e., reading the raw sensor data, generating features, and activity classification using a deep neural network (DNN). It achieves 95% accuracy in recognizing 8 common human activities while providing three orders of magnitude higher energy efficiency compared to existing solutions.

关键词： Human activity recognition wearable electronics flexible hybrid electronics hardware accelerator low-power design health monitoring

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proceedings of the international conference on Embedded software Companion, EMSOFT 2019

Proceedings of the International Conference on Embedded Soft...

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2019 international conference on Embedded software, EMSOFT 2019

ISBN: (纸本)9781450369244

The proceedings contain 13 papers. The topics discussed include: deriving equations from sensor data using dimensional function synthesis;a dual-mode strategy for performance-maximization and resource-efficient CPS design;coherent extension, composition, and merging operators in contract models for system design;efficient decentralized LTL monitoring framework using tableau technique;will my program break on this faulty processor? - formal analysis of hardware fault activations in concurrent embedded software;and timing-anomaly free dynamic scheduling of conditional DAG tasks on multi-core systems.

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Work-in-Progress: EAST-DNN: Expediting Architectural SimulaTions Using Deep Neural Networks

Work-in-Progress: EAST-DNN: Expediting Architectural SimulaT...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Arko Dutt Govind Narasimman Lin Jie Vijay Ramaseshan Chandrasekhar Mohamed M. Sabry NTU Singapore A*STAR I2R Singapore

A rapid and accurate architectural simulator is a cornerstone for an emcient design-space exploration of computing systems. In this paper, we introduce EAST-DNN, a feed-forward deep neural network, to accelerate architectural simulations. EAST-DNN achieves > 10 6 × speedup with an average prediction error of 4.3% over the baseline simulator. It also achieves an average of 2× better accuracy with at least 2.3× speedup compared to state-of-the-art.

关键词： Radio frequency Neural networks Acceleration hardware Boosting Training Computational modeling

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Deriving Equations from Sensor Data Using Dimensional Function synthesis

Deriving Equations from Sensor Data Using Dimensional Functi...

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作者： Wang, Youchao Willis, Sam Tsoutsouras, Vasileios Stanley-Marbell, Phillip Univ Cambridge 9 JJ Thomson Ave Cambridge CB3 0FA England

We present a new method for deriving functions that model the relationship between multiple signals in a physical system. The method, which we call dimensional function synthesis, applies to data streams where the dimensions of the signals are known. The method comprises two phases: a compile-time synthesis phase and a subsequent calibration using sensor data. We implement dimensional function synthesis and use the implementation to demonstrate efficiently summarizing multi-modal sensor data for two physical systems using 90 laboratory experiments and 10 000 synthetic idealized measurements. We evaluate the performance of the compile-time phase of dimensional function synthesis as well as the calibration phase overhead, inference latency, and accuracy of the models our method generates. The results show that our technique can generate models in less than 300 ms on average across all the physical systems we evaluated. When calibrated with sensor data, our models outperform traditional regression and neural network models in inference accuracy in all the cases we evaluated. In addition, our models perform better in training latency (over 8660x improvement) and required arithmetic operations in inference (over 34x improvement). These significant gains are largely the result of exploiting information on the physics of signals that has hitherto been ignored.

关键词： Machine learning dimensional analysis sensor data fusion

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