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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1556 条记录，以下是171-180 订阅

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Work-in-Progress: Drama: A High Efficient Neural Network Accelerator on FPGA using Dynamic Reconfiguration

Work-in-Progress: Drama: A High Efficient Neural Network Acc...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Yang Yang Chao Wang Xuehai Zhou University of Science and Technology of China Suzhou China

In this paper, we propose a high efficient neural network accelerator on FPGA by using dynamic reconfiguration, named Drama. Firstly, we design a high-efficient hardware architecture and provide a hardware template that can generate optimal configuration for each layer. Then, to explore the key features of the neural network models, we employ a layer-clustering algorithm to classify different layers. After that, we transform CNN models into task sequences. To accomplish the execution of the sequence, the FPGA-based hardware is able to switch the accelerator with dynamic reconfiguration and offload the related tasks to the accelerator at runtime. Preliminary results on the FPGA platform demonstrate that Drama is able to improve the performance significantly due to the dynamic reconfiguration techniques.

关键词： Field programmable gate arrays hardware Neural networks Task analysis Parallel processing Bandwidth Runtime

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Polar: Function Code Aware Fuzz Testing of ICS Protocol

Polar: Function Code Aware Fuzz Testing of ICS Protocol

引用

Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Luo, Zhengxiong Zuo, Feilong Jiang, Yu Gao, Jian Jiao, Xun Sun, Jiaguang Tsinghua Univ Sch Software BNRist KLISS Beijing Peoples R China Villanova Univ Dept Comp Sci & Engn Villanova PA 19085 USA

Industrial Control system (ICS) protocols are widely used to build communications among system components. Compared with common internet protocols, ICS protocols have more control over remote devices by carrying a specific field called "function code", which assigns what the receive end should do. Therefore, it is of vital importance to ensure their correctness. However, traditional vulnerability detection techniques such as fuzz testing are challenged by the increasing complexity of these diverse ICS protocols. In this paper, we present a function code aware fuzzing framework - Polar, which automatically extracts semantic information from the ICS protocol and utilizes this information to accelerate security vulnerability detection. Based on static analysis and dynamic taint analysis, Polar initiates the values of the function code field and identifies some vulnerable operations. Then, novel semantic aware mutation and selection strategies are designed to optimize the fuzzing procedure. For evaluation, we implement Polar on top of two popular fuzzers - AFL and AFLFast, and conduct experiments on several widely used ICS protocols such as Modbus, IEC104, and IEC 61850. Results show that, compared with AFL and AFLFast, Polar achieves the same code coverage and bug detection numbers at the speed of 1.5X-12X. It also gains increase with 0%-91% more paths within 24 hours. Furthermore, Polar has exposed 10 previously unknown vulnerabilities in those protocols, 6 of which have been assigned unique CVE identifiers in the US National Vulnerability Database.

关键词： Fuzz testing industrial control system protocol function code vulnerability detection

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Work-in-Progress: A Simulation Framework for Domain-Specific system-on-Chips

Work-in-Progress: A Simulation Framework for Domain-Specific...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Samet E. Arda NK Anish A. Alper Goksoy Joshua Mack Nirmal Kumbhare Anderson L. Sartor Ali Akoglu Radu Marculescu Umit Y. Ogras School of Electrical Computer and Energy Engineering Arizona State University Tempe AZ USA Electrical and Computer Engineering The University of Arizona Tucson AZ USA Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

Homogeneous general purpose processors provide flexibility to implement a variety of applications and facilitate programmability. In contrast, heterogeneous system-on-chips (SoCs) that combine general purpose and specialized processors offer great potential to achieve higher efficiency while maintaining programming flexibility. In particular, domain-specific SoCs (DSSoC), a class of heterogeneous architectures, tailor the architecture and processing elements (PE) to a specific domain. Hence, they can provide superior energy-efficiency compared to general purpose processors by exploiting the characteristics of target applications.

关键词： Task analysis Schedules Computer architecture Heuristic algorithms Dynamic scheduling hardware

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Work-in-Progress: A concept of a hardware design environment with the functional language Elixir

Work-in-Progress: A concept of a hardware design environment...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hideki Takase Kentaro Matsui Yoshihiro Ueno Masakazu Mori Yuki Hisae Susumu Yamazaki JST PRESTO Japan Kyoto University Sakyo-ku Kyoto Japan Delight Systems Co. Ltd. Chuo-ku Fukuoka Japan Karabiner Technology Inc. Chuo-ku Fukuoka Japan The University of Kitakyushu Wakamatsu-ku Kitakushu Japan

The functional language Elixir is designed to be effective for the application. One of the most considerable feature of Elixir is that it is easy to realize the parallel processing with the standard library, such as Flow. In this paper, we study a design environment for hardware circuits using Elixir as a design language. We propose a synthesize flow for data flow hardware on the FPGA from the native Elixir code. Our method synthesizes functional equivalence circuits from the description of Enum and Flow in Elixir, which are libraries for direct manipulation and parallel processing of data collection in Elixir. Data flow is implemented base on the pipeline operator which connects the processing relation of the function by the data processing order. To realize a hardware design environment by Elixir, this paper shares current status of our implementation.

关键词： hardware Field programmable gate arrays hardware design languages Distributed databases IP networks Parallel processing Pipelines

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High-Level synthesis of Approximate Designs under Real-Time Constraints

High-Level Synthesis of Approximate Designs under Real-Time ...

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作者： Leipnitz, Marcos T. Nazar, Gabriel L. Univ Fed Rio Grande do Sul Informat Inst Av Bento Goncalves 9500 BR-91501970 Porto Alegre RS Brazil

The adoption of High-Level synthesis (HLS) has increased as the latest HLS tools have evolved to provide high-quality results while improving productivity and time-to-market. Concurrently, many works have been proposing the incorporation of approximate computing techniques within HLS toolchains, allowing automated generation of inexact circuits for error-tolerant application domains with the aim of trading-off computation accuracy with area/power savings or performance improvements. Thus, when attempting to make a design meet timing requirements, designers of real-time systems using HLS may resort to approximation approaches. However, current approximate HLS tools do not allow specifying real-time constraints, being instead error-constrained to explore area, power, or performance optimizations. In this work, we propose an approximate HLS framework for real-time systems that can be integrated with state-of-the-art HLS tools. With this framework designers can specify real-time constraints and satisfy them while minimizing the output error. It uses scheduling information and Worst-Case Execution Time (WCET) analysis for iteratively exploring time-error trade-offs of approximations in the time-critical execution path. Experimental results on signal and image processing benchmarks show that we can reduce the WCET of exact designs by up to 35% with acceptable quality degradation.

关键词： High-level synthesis approximate computing worst-case execution time design space exploration

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Work-in-Progress: Runtime Requirements Monitoring for State-based hardware

Work-in-Progress: Runtime Requirements Monitoring for State-...

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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Seo, Minjun Lysecky, Roman Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA

ISBN: (纸本)9781538655627

This paper presents a requirements-driven methodology enabling efficient runtime monitoring of hardware in embedded systems. We present a novel method for extracting hardware verification requirements from state-based hardware models to construct a hierarchical runtime monitoring graph (HRMG) that can be efficiently used at runtime to verify correctness.

关键词： Runtime requirements verification hardware verification formal verification models non-intrusive monitoring

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Statistical Verification of Hyperproperties for Cyber-Physical systems

Statistical Verification of Hyperproperties for Cyber-Physic...

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作者： Wang, Yu Zarei, Mojtaba Bonakdarpour, Borzoo Pajic, Miroslav Duke Univ 100 Sci DrHudson Hall Rm 220 Durham NC 27708 USA Iowa State Univ 207 Atanasoff Hall Ames IA 50011 USA

Many important properties of cyber-physical systems (CPS) are defined upon the relationship between multiple executions simultaneously in continuous time. Examples include probabilistic fairness and sensitivity to modeling errors (i.e., parameters changes) for real-valued signals. These requirements can only be specified by hyperproperties. In this article, we focus on verifying probabilistic hyperproperties for CPS. To cover a wide range of modeling formalisms, we first propose a general model of probabilistic uncertain systems (PUSs) that unify commonly studied CPS models such as continuous-time Markov chains (CTMCs) and probabilistically parametrized Hybrid I/O Automata (P(2)HIOA). To formally specify hyperproperties, we propose a new temporal logic, hyper probabilistic signal temporal logic (HyperPSTL) that serves as a hyper and probabilistic version of the conventional signal temporal logic (STL). Considering the complexity of real-world systems that can be captured as PUSs, we adopt a statistical model checking (SMC) approach for their verification. We develop a new SMC technique based on the direct computation of significance levels of statistical assertions for HyperPSTL specifications, which requires no a priori knowledge on the indifference margin. Then, we introduce SMC algorithms for HyperPSTL specifications on the joint probabilistic distribution of multiple paths, as well as specifications with nested probabilistic operators quantifying different paths, which cannot be handled by existing SMC algorithms. Finally, we show the effectiveness of our SMC algorithms on CPS benchmarks with varying levels of complexity, including the Toyota Powertrain Control system.

关键词： Cyber-physical systems hyperproperties statistical model checking embedded control software

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Work-in-Progress: hardware Implementation of a Multi-Mode-Aware Mixed-Criticality Scheduler

Work-in-Progress: Hardware Implementation of a Multi-Mode-Aw...

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ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Hounsinou, Sena Vasu, Aishwarya Ramaprasad, Harini Southern Illinois Univ Carbondale IL 62901 USA Univ N Carolina Charlotte NC USA

ISBN: (纸本)9781538655627

To minimize size, weight, power, and cost, the industry aims at consolidating different criticality applications on the same hardware platform. In such a mixed-criticality environment, it is challenging to contain the overhead due to potential mode changes under overload conditions. Traditional scheduler implementation at the software level introduces additional overheads due to timer interrupt processing and context switching. To minimize overall software overhead and to improve timing predictability, in this paper, we propose an implementation of the mixed-criticality scheduler in the hardware that is capable of detecting task-overruns and making mode transitions seamlessly.

关键词： Task analysis hardware Real-time systems Monitoring Registers software Processor scheduling

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2015 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2015

2015 International Conference on Hardware/Software Codesign ...

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international conference on hardware/software codesign and system synthesis, CODES+ISSS 2015

ISBN: (纸本)9781467383219

The proceedings contain 24 papers. The topics discussed include: how to improve the space utilization of Dedup-based PCM storage devices?;a tiny-capacitor-backed non-volatile buffer to reduce storage writes in smartphones;lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs;improved hard real-time scheduling of CSDF-modeled streaming applications;hardware synthesis from a recursive functional language;power-awareness and smart-resource management in embedded computing systems;an online wear state monitoring methodology for off-the-shelf embedded processors;big/little deep neural network for ultra low power inference;an approximate compressor for wearable biomedical healthcare monitoring systems;and fast parallel application and multiprocessor design space exploration from sequential code.

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SWARAM: Portable Energy and Cost Efficient Embedded system for Genomic Processing

SWARAM: Portable Energy and Cost Efficient Embedded System f...

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作者： Mohanty, Ram Prasad Gamaarachchi, Hasindu Lambert, Andrew Parameswaran, Sri Univ New South Wales Canberra ACT 2612 Australia Univ New South Wales Sydney NSW 2052 Australia

Treatment of patients using high-quality precision medicine requires a thorough understanding of the genetic composition of a patient. Ideally, the identification of unique variations in an individual's genome is needed for specifying the necessary treatment. Variant calling workflow is a pipeline of tools, integrating state of the art software systems aimed at alignment, sorting and variant calling for the whole genome sequencing (WGS) data. This pipeline is utilized for identifying unique variations in an individual's genome (compared to a reference genome). Currently, such a workflow is implemented on high-performance computers (with additional GPUs or FPGAs) or in cloud computers. Such systems are large, have a high cost, and rely on the internet for genome data transfer which makes the system unusable in remote locations unequipped with internet connectivity. It further raises privacy concerns due to processing being carried out in a different facility. To overcome such limitations, in this paper, for the first time, we present a cost-efficient, offline, scalable, portable, and energy-efficient computing system named SWARAM for variant calling workflow processing. The system uses novel architecture and algorithms to match against partial reference genomes to exploit smaller memory sizes which are typically available in tiny processing systems. Extensive tests on a standard benchmark data-set (NA12878 Illumina platinum genome) confirm that the time consumed for the data transfer and completing variant calling workflow on SWARAM was competitive to that of a 32-core Intel Xeon server with similar accuracy, but costs less than a fifth, and consumes less than 40% of the energy of the server system. The original scripts and code we developed for executing the variant calling workflow on SWARAM are available in the associated Github repository https://***/Rammohanty/swaram.

关键词： Genome alignment variant calling genetic analysis embedded system ARM DNA analysis energy efficient system portable genome analysis

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