检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,501 篇 会议
55 篇 期刊文献

馆藏范围

1,556 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

801 篇 工学
- 740 篇 计算机科学与技术...
- 561 篇 软件工程
- 154 篇 电气工程
- 135 篇 电子科学与技术（可...
- 103 篇 信息与通信工程
- 75 篇 控制科学与工程
- 22 篇 机械工程
- 13 篇 动力工程及工程热...
- 12 篇 光学工程
- 10 篇 建筑学
- 9 篇 仪器科学与技术
- 9 篇 生物工程
- 8 篇 材料科学与工程（可...
- 8 篇 土木工程
- 8 篇 生物医学工程（可授...
- 8 篇 安全科学与工程
- 6 篇 航空宇航科学与技...
180 篇 理学
- 104 篇 数学
- 48 篇 系统科学
- 40 篇 物理学
- 16 篇 统计学（可授理学、...
- 9 篇 生物学
- 6 篇 化学
109 篇 管理学
- 90 篇 管理科学与工程(可...
- 29 篇 工商管理
- 23 篇 图书情报与档案管...
15 篇 法学
- 11 篇 社会学
5 篇 经济学
- 5 篇 应用经济学
5 篇 教育学
- 5 篇 教育学
5 篇 医学
- 5 篇 临床医学
4 篇 艺术学
1 篇 农学

主题

359 篇 hardware
177 篇 computer archite...
162 篇 embedded system
135 篇 application soft...
87 篇 field programmab...
83 篇 embedded systems
75 篇 control system s...
69 篇 costs
67 篇 high level synth...
65 篇 computational mo...
65 篇 algorithm design...
64 篇 system-on-a-chip
63 篇 permission
63 篇 embedded softwar...
61 篇 real time system...
52 篇 timing
50 篇 system-on-chip
48 篇 computer science
47 篇 energy consumpti...
46 篇 space exploratio...

机构

10 篇 department of el...
8 篇 univ calif river...
8 篇 center for embed...
6 篇 school of comput...
6 篇 arizona state un...
6 篇 center for embed...
6 篇 department of co...
5 篇 princeton univ d...
5 篇 school of inform...
5 篇 department of co...
5 篇 philips research...
5 篇 institute for in...
5 篇 technische unive...
4 篇 department of el...
4 篇 ibm thomas j. wa...
4 篇 imec leuven
4 篇 politecn torino ...
4 篇 university of er...
4 篇 tu braunschweig
4 篇 university of do...

作者

9 篇 sri parameswaran
9 篇 ogras umit y.
9 篇 parameswaran sri
9 篇 nikil dutt
7 篇 rolf ernst
7 篇 dick robert p.
7 篇 dutt nikil
7 篇 robert p. dick
7 篇 leupers rainer
7 篇 vahid f
6 篇 jiang wei
6 篇 greg stitt
6 篇 teich juergen
6 篇 mitra tulika
6 篇 rainer leupers
6 篇 andreas gerstlau...
6 篇 a. sangiovanni-v...
6 篇 r. ernst
6 篇 jha niraj k.
5 篇 sungjoo yoo

语言

1,528 篇 英文
26 篇 其他
2 篇 中文

检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1556 条记录，以下是181-190 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction: work-in-progress 19

Offloading cache configuration prediction to an FPGA for har...

引用

proceedings of the international conference on hardware/software codesign and system synthesis Companion

作者： Ruben Vazquez Ann Gordon-Ross Greg Stitt University of Florida

In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and hardware overhead reduction, while maintaining cache configuration predictions within 5% of th... 详细信息

ISBN: (纸本)9781450369237

关键词： configurable artificial neural network machine learning cache phases mobile devices FPGA

来源：评论

学校读者我要写书评

暂无评论

Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs 19

Synetgy: Algorithm-hardware Co-design for ConvNet Accelerato...

引用

ACM/SIGDA international Symposium on Field-Programmable Gate Arrays (FPGA)

作者： Yang, Yifan Huang, Qijing Wu, Bichen Zhang, Tianjun Ma, Liang Gambardella, Giulio Blott, Michaela Lavagno, Luciano Vissers, Kees Wawrzynek, John Keutzer, Kurt Univ Calif Berkeley Berkeley CA 94720 USA Tsinghua Univ Beijing Peoples R China Politecn Torino Turin Italy Xilinx Res Labs San Jose CA USA

ISBN: (纸本)9781450361378

Using FPGAs to accelerate ConvNets has attracted significant attention in recent years. However, FPGA accelerator design has not leveraged the latest progress of ConvNets. As a result, the key application characteristics such as frames-per-second (FPS) are ignored in favor of simply counting GOPs, and results on accuracy, which is critical to application success, are often not even reported. In this work, we adopt an algorithm-hardware co-design approach to develop a ConvNet accelerator called Synetgy and a novel ConvNet model called DiracDeltaNet(dagger). Both the accelerator and ConvNet are tailored to FPGA requirements. DiracDeltaNet, as the name suggests, is a ConvNet with only 1 x 1 convolutions while spatial convolutions are replaced by more efficient shift operations. DiracDeltaNet achieves competitive accuracy on ImageNet (89.0% top-5), but with 48x fewer parameters and 65x fewer OPs than VGG16. We further quantize DiracDeltaNet's weights to 1-bit and activations to 4-bits, with less than 1% accuracy loss. These quantizations exploit well the nature of FPGA hardware. In short, DiracDeltaNet's small model size, low computational OP count, ultra-low precision and simplified operators allow us to co-design a highly customized computing unit for an FPGA. We implement the computing units for DiracDeltaNet on an Ultra96 SoC system through high-level synthesis. Our accelerator's final top-5 accuracy of 88.2% on ImageNet, is higher than all the previously reported embedded FPGA accelerators. In addition, the accelerator reaches an inference speed of 96.5 FPS on the ImageNet classification task, surpassing prior works with similar accuracy by at least 16.9x.

关键词： imagenet classification hardware accelerators hardware-software codesign fpga embedded hardware computer vision problems neural networks

来源：评论

学校读者我要写书评

暂无评论

Special Session: Future Automotive systems Design: Research Challenges and Opportunities

Special Session: Future Automotive Systems Design: Research ...

引用

ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Saidi, Selma Steinhorst, Sebastian Hamann, Arne Ziegenbein, Dirk Wolf, Marko Hamburg Univ Technol Hamburg Germany Tech Univ Munich Munich Germany Robert Bosch GmbH Renningen Germany ESCRYPT GmbH Munich Germany

ISBN: (纸本)9781538655627

Automotive systems are currently undergoing a radical shift in the way they are designed, implemented and deployed. Such changes impose an increased complexity and a high number of requirements in order to be more automated, connected, dependable and cost-effective. This raises several challenges that the embedded systems community has to face, encountered at different stages of systems development from modeling and design to software/hardware deployment and validation. This paper discusses current industrial trends and open problems in the hardware and software design of automotive systems, dictating rigorous constraints in terms of safety, real-time capabilities and security which have to be considered in future automotive systems design.

关键词： Automotive engineering software Computer architecture hardware system analysis and design Market research Safety

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: AMVP - A High Performance Virtual Platform using Parallel systemC for Multicore ARM Architectures

Work-in-Progress: AMVP - A High Performance Virtual Platform...

引用

ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Weinstock, Jan Henrik Bucs, Robert Lajos Walbroel, Florian Leupers, Rainer Ascheid, Gerd Rhein Westfal TH Aachen Aachen Germany

ISBN: (纸本)9781538655627

This paper presents AMVP - a systemC based simulator for ARM multicore platforms designed as a tool for early SW development during platform bring-up. It uses a parallel systemC simulation approach to counter the performance slowdown incurred when simulating multi-processor designs. AMVP is sufficiently detailed to support running and debugging unmodified SW images of popular benchmark applications and modern OS kernels like Linux.

关键词： Electronic system Level Parallel Discrete Event Simulation Parallel systemC Simulation

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: Co-Design of Security-Critical Real-Time systems to Prevent Fault Injection Attacks

Work-in-Progress: Co-Design of Security-Critical Real-Time S...

引用

ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Jiang, Wei Xiu, Liugen Zhan, Jinyu Jiang, Ke Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China Veoneer Res & Engn Dept Stockholm Sweden

ISBN: (纸本)9781538655627

We present a system-level co-design approach for security-critical real-time systems to resist fault injection attack. We focus on protecting the encryption/decryption of confidential messages over the internal communication in distributed real-time systems. To achieve the goal, we identify ten mechanisms of Fault Detection and Correction (FDC) and measure their corresponding time overheads and hardware overheads. We then make efforts to search for the best FDC schemes for protecting the message communication without violating the application deadline and hardware budget. We propose an efficient heuristic based on multi-objective evolutionary algorithms, which obtains better solutions with lower time complexity. Experiments demonstrate the superiority of the proposed technique.

关键词： Field programmable gate arrays Task analysis Cryptography Real-time systems Fault detection Resists

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: Hierarchical Ensemble Learning for Resource-Aware FPGA Computing

Work-in-Progress: Hierarchical Ensemble Learning for Resourc...

引用

ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Wang, Hongfei Li, Jianwen He, Kun Cai, Wenjie Huazhong Univ Sci & Technol Sch Comp Sci & Technol Wuhan Peoples R China

ISBN: (纸本)9781538655627

Recent years witness the rapid development in hardware/software codesign that integrates machine learning (ML) models with hardware systems [1]–[4]. Despite the booming trend in building neuromorphic computing systems [2], decision trees still attract much attention in ML communities, from both software [5], [6] and hardware [1], [7], [8] approaches. A single tree model may not be as accurate as desired. One effective way to remedy this is to apply ensemble methods [5]–[7], [9]–[11], such as the Random Forest (RF) [5]. Larger tree ensembles typically improve accuracy, but demand more computation resources, especially for hardware implementation. Many methods have been proposed to address this issue. The motivation arouses from the fact that tree models usually demands much less computation resource comparing to neural networks, making them extremely potential for wearable devices and embedded systems at the edge nodes of the IoT [7], [11], [12]. Moreover, due to their inherent structures, tree ensembles are ideal for exploiting the computational parallelism on FPGA [1], [4], [7]–[9], [11], [13].

关键词： Radio frequency Vegetation hardware Field programmable gate arrays Forestry Minimization Computational modeling

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: Equivalence of Transformations of Synchronous Data Flow Graphs

Work-in-Progress: Equivalence of Transformations of Synchron...

引用

ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Zhu, Xue-Yang Chinese Acad Sci State Key Lab Comp Sci Inst Software Beijing Peoples R China

ISBN: (纸本)9781538655627

Synchronous data flow graphs (SDFGs) are widely used to model digital signal processing (DSP) algorithms and streaming applications. Any valid SDFG can be converted to an equivalent homogenous SDFG (HSDFG). Retiming and unfolding are important graph transformation techniques for performance optimization of SDFGs. In this paper, we review the relationship among the three transformation techniques and reveal the equivalence of the combinations of them. The equivalence makes it possible to analyze and optimize SDFGs directly, without carrying out the explicit conversion procedures which are usually time and space-consuming.

关键词： IP networks Computational modeling Signal processing algorithms Processor scheduling Digital signal processing Optimization

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: On Leveraging Approximations for Exact system-level Design Space Exploration

Work-in-Progress: On Leveraging Approximations for Exact Sys...

引用

ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Neubauer, Kai Haubelt, Christian Wanko, Philipp Schaub, Torsten Univ Rostock Rostock Germany Univ Potsdam Potsdam Germany

ISBN: (纸本)9781538655627

In order to find good design points for embedded systems, an efficient exploration of the design space is imperative. The ever-increasing complexity of embedded systems, however, results in a deterioration of the overall exploration performance. The DSE essentially consists of two parts: (1) the search for feasible solutions and (2) the evaluation of found feasible solutions. While the search has been massively improved by ASPmT-based strategies, the evaluation emerges as the main bottleneck. Tragically, evaluating bad solutions takes as much time as evaluating good ones. Hence, in this paper we study the utilization of approximations in the evaluation process integrated in an ASPmT-based DSE to identify bad solutions more quickly while still retaining the exact Pareto-front.

关键词： Design Space Exploration system-level Design Approximation

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: A Chip-Level Security Framework for Assessing Sensor Data Integrity

Work-in-Progress: A Chip-Level Security Framework for Assess...

引用

ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Wehbe, Taimour Mooney, Vincent J. Keezer, David C. Georgia Inst Technol Atlanta GA 30332 USA

ISBN: (纸本)9781538655627

The continuously increasing inter-connectivity of sensor nodes that form the basis of the Internet-of-Things results in new avenues of attack exploitable by adversaries to maliciously modify data captured by these nodes. In this work, we present a framework for detecting malicious hardware alterations that attempt to attack state-of-the-art microchips that form these sensor nodes. Specifically, we focus on extremely small hardware Trojans (HTs) that attempt to modify sensor data right away as the data is received on a state-of-the-art chip fabricated in an untrusted facility. We present a dual-chip approach composed of an untrusted state-of-the-art prover chip and a trusted verifier chip, where the verifier continuously challenges the prover at run-time to ensure correct operation and assess the integrity of the captured data. Our preliminary analysis of the proposed mechanism shows that HT attacks anywhere on the untrusted state-of-the-art chip are detected and flagged preventing maliciously altered data to be transmitted out of the sensor node.

关键词： security in hardware hardware attacks and countermeasures malicious design modifications embedded systems security sensor networks hardware Trojans data integrity

来源：评论

学校读者我要写书评

暂无评论

EAST-DNN: Expediting architectural SimulaTions using deep neural networks: work-in-progress 19

EAST-DNN: Expediting architectural SimulaTions using deep ne...

引用

proceedings of the international conference on hardware/software codesign and system synthesis Companion

作者： Arko Dutt Govind Narasimman Lin Jie Vijay Ramaseshan Chandrasekhar Mohamed M. Sabry NTU Singapore ASTAR IR Singapore

ISBN: (纸本)9781450369237

A rapid and accurate architectural simulator is a cornerstone for an efficient design-space exploration of computing systems. In this paper, we introduce EAST-DNN, a feed-forward deep neural network, to accelerate architectural simulations. EAST-DNN achieves > 106X speedup with an average prediction error of 4.3% over the baseline simulator. It also achieves an average of 2X better accuracy with at least 2.3X speedup compared to state-of-the-art.

关键词： deep neural network hardware accelerators

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共156页 << < 15 16 17 18 19 20 21 22 23 24 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：