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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1553 条记录，以下是11-20 订阅

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2018 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2018

2018 International Conference on Hardware/Software Codesign ...

引用

2018 ACM/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2018

ISBN: (纸本)9781538655627

The proceedings contain 20 papers. The topics discussed include: work-in-progress: a chip-level security framework for assessing sensor data integrity;work-in-progress: equivalence of transformations of synchronous data flow graphs;special session: future automotive systems design: research challenges and opportunities;work-in-progress: runtime requirements monitoring for state-based hardware;work-in-progress: introducing assume-guarantee contracts for verifying robotic applications;work-in-progress: AMVP - a high performance virtual platform using parallel systemC for multicore ARM architectures;work-in-progress: hierarchical ensemble learning for resource-aware FPGA computing;and work-in-progress: WinoNN: optimizing FPGA-based neural network accelerators using fast Winograd algorithm.

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Special Session: Emerging Architecture Design, Control, and Security Challenges in software Defined Vehicles

Special Session: Emerging Architecture Design, Control, and ...

引用

2024 international conference on hardware/software codesign and system synthesis

作者： El-Fatyany, Aya Wang, Xiaohang Duggirala, Parasara Sridhar Chakraborty, Samarjit Pasricha, Sudeep Singh, Amit Kumar Zhejiang Univ Hangzhou Peoples R China Menoufia Univ Shibin Al Kawm Egypt UNC Chapel Hill Chapel Hill NC USA Colorado State Univ Ft Collins CO USA Univ Essex Colchester England

ISBN: (纸本)9798350356403;9798350356397

software Defined Vehicles (SDVs) represent a paradigm shift in the automotive industry, where vehicles are increasingly controlled and managed through software, while relying less on mechanical and hardware components. While this allows considerable flexibility in the introduction of new "smart" features and fast tracks innovations in multiple domains, it also creates new challenges and opportunities in architecture design, control, and security. By adopting modular architectures, adaptive control strategies, and robust security measures, SDVs can pave the way for a safer and more efficient future of transportation. In this paper, we cover perspectives from both, industry and academia, in this area. They provide embedded systems researchers an overview of recent developments and emerging challenges in SDV from the perspective of architecture design, control, and security. The emerging challenges also set the foundations for future research in this domain.

关键词： software defined vehicles (SDVs) Architecture design Control Robustness Security

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CoChrono: A Unified hardware/software Performance Analysis Tool for SoC-FPGA codesign 22

CoChrono: A Unified Hardware/Software Performance Analysis T...

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22nd IEEE Interregional NEWCAS conference (NEWCAS)

作者： Portas, Fabien Bois, Guy Savaria, Yvon Polytech Montreal Comp Engn Dept Montreal PQ Canada Polytech Montreal Elect Engn Dept Montreal PQ Canada

ISBN: (纸本)9798350361766;9798350361759

High-level embedded system design tools are making the design of complex SoC-FPGA systems more accessible than ever before. However, this comes at the cost of more opacity as implementations result from heavy transformations made by high-level synthesis tools, while there is a lack of complete suitable performance analysis tools for the resulting implementations. This paper proposes a unified application programmer interface and methodology that enables the extraction of time points to instrument performance metrics for hardware/software co-simulation and monitoring the SoC-FPGA execution. The proposed tool, called CoChrono, leverages high-level synthesis and code generation to access metrics similarly in software and hardware C++ code. The tool's features and low overhead are demonstrated with a practical application of architecture exploration and simulation model validation. Compared to instruments manually inserted using existing tools, CoChrono significantly reduces the effort required to validate complex timing constraints in hardware/software systems.

关键词： monitoring instrumentation SoC-FPGA HLS performance metrics HW/SW codesign system-level design

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Exploring Compositional Neural Networks for Real-Time systems 22

Exploring Compositional Neural Networks for Real-Time System...

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22nd international conference on Formal Methods and Models for system Design

作者： Chatterjee, Sobhan Allen, Nathan Patel, Nitish Roop, Partha Univ Auckland Fac Engn Dept Elect Comp & Software Engn Auckland New Zealand

ISBN: (纸本)9798350378030;9798350378023

Real-time CPSs using Artificial Neural Networks (ANNs) are traditionally developed as monolithic black-boxes. This results in designs that are often difficult to formally verify against safety specifications and implement on hardware for formal timing analysis. Consequently, their implementation as a composition of smaller ANNs has received recent interest. These are easier to implement, parallelise and validate. Despite this, the question of how to produce hardware-implementable compositional designs from existing monolithic ones remains largely unanswered. This work develops a novel procedure to replace large ANN monolithic designs with smaller compositional designs and implement them on a Field Programmable Gate Array (FPGA) for timing analysis using synchronous compositional semantics. To illustrate our approach, we develop regression and classification ANN designs for multiple real-life datasets. Using various design and model architecture variations, we show that using a compositional design instead of a monolithic design can achieve an 85% reduction in WCET, around a 53% reduction in hardware resources and around a 40% reduction in computations and neuron connections for a minor reduction in performance.

关键词： Compositional Design FPGA hardware synthesis Lane Change Neural Network Neural Network Optimisation Neutal Network Composition

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Higher-order hardware: Implementation and Evaluation of the Cephalopode Graph Reduction Processor 22

Higher-order Hardware: Implementation and Evaluation of the ...

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22nd international conference on Formal Methods and Models for system Design

作者： Pope, Jeremy Seger, Carl-Johan H. Valter, Henrik Chalmers Univ Technol Dept CSE Gothenburg Sweden

ISBN: (纸本)9798350378030;9798350378023

A major challenge with the practical deployment of Internet-of-Things (IoTs) is how to develop the high-quality code needed in order to produce robust and secure IoT devices. In other domains, high-level programming languages have shown to be efficient vehicles towards this. However, the very limited compute power provided by IoT devices have made it difficult to apply the same approach to IoT devices. The Cephalopode processor is an attempt at implementing a low power hardware device directly aimed at running a high-level functional language. By integrating many resource-heavy tasks like garbage collection and arbitrary precision arithmetic into dedicated hardware, the Cephalopode processor explores the hypothesis that high-level functional languages can be used even for low-power IoT devices. This paper presents the implementation and evaluation of the Cephalopode processor. We discuss the approach taken, the compiler and the architecture of the processor. We also describe the design process and design considerations. After implementation and synthesis we compare the processor to a conventional RISC-V processor running a functional language software environment. We also compare Cephalopode with running handwritten C code on the RISC-V processor.

关键词： Program compilers

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Work-in-Progress: A Generic Non-Intrusive Parallelization Approach for systemC TlM-2.0-Based Virtual Platforms

Work-in-Progress: A Generic Non-Intrusive Parallelization Ap...

引用

2023 ACM/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2023

作者： Bosbach, Nils Pelke, Rebecca Zurstrassen, Niko Junger, Lukas Weinstock, Jan Henrik Leupers, Rainer Rwth Aachen University Aachen Germany MachineWare GmbH Aachen Germany

ISBN: (纸本)9798400702891

The ever-growing complexity of systems-on-a-Chip (SoCs) requires continuous improvements of development tools such as Virtual Platforms (VPs). VPs are software (SW)-based functional simulators of SoCs that allow SW development in an early design stage. Any improvement of VP's performance reduces the needed simulation time and thereby accelerates the development process. In this work, we present a novel approach that can be used to parallelize the CPU model of a systemC-TLM-2.0-based VP. We present our first results showing that the technique can achieve speedups of up to 7. 5x for an octa-core ARM VP. © 2023 ACM.

关键词： system-on-chip

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Work-in-Progress: BloCirNN: An Efficient software/hardware codesign Approach for Neural Network Accelerators with Block-Circulant Matrix

Work-in-Progress: BloCirNN: An Efficient Software/hardware C...

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ACM/IEEE international conference on hardware/software codesign and system synthesis part of the Embedded systems Week (ESWEEK)

作者： Qin, Yunji Gong, Lei Zheng, Zhendong Wang, Chao Univ Sci & Technol China Sch Comp Sci & Technol Hefei Peoples R China

ISBN: (数字)9781665472944

ISBN: (纸本)9781665472944

Nowadays, the scale of deep neural networks is getting larger and larger. These large-scale deep neural networks are both compute and memory intensive. To overcome these problems, we use block-circulant weight matrices and Fast Fourier Transform (FFT) to compress model and optimize computation. Compared to weight pruning, this method does not suffer from irregular networks. The main contributions of this paper include the implementation of a convolution module and a fully-connected module with High-Level synthesis (HLS), deployment and performance test on FPGA platform. We use AlexNet as a case study, which demonstrates our design is more efficient than the FPGA2016.

关键词： block-circulant matrix compression FPGA Accelerator

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proceedings of the 11th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES 2016

Proceedings of the 11th IEEE/ACM/IFIP International Conferen...

引用

11th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES 2016

ISBN: (纸本)9781450344838

The proceedings contain 37 papers. The topics discussed include: a practical methodology to validate the statistical behavior of bloom filters;scalable and realistic benchmark synthesis for efficient NoC performance evaluation: a complex network analysis approach;an accurate and flexible early memory system power evaluation approach using a microcomponent method;time and timeliness;a design to reduce write amplification in object-based NAND flash devices;enabling the high level synthesis of data analytics accelerators;and going deeper than deep learning for massive data analytics under physical constraints.

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Work-in-Progress: What to Expect of Early Training Statistics? An Investigation on hardware-Aware Neural Architecture Search

Work-in-Progress: What to Expect of Early Training Statistic...

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ACM/IEEE international conference on hardware/software codesign and system synthesis part of the Embedded systems Week (ESWEEK)

作者： Luo, Xiangzhong Liu, Di Kong, Hao Huai, Shuo Chen, Hui Liu, Weichen Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore Nanyang Technol Univ HP NTU Digital Mfg Corp Lab Singapore Singapore

ISBN: (数字)9781665472944

ISBN: (纸本)9781665472944

Neural architecture search (NAS) is an emerging paradigm to automate the design of top-performing deep neural networks (DNNs). Specifically, the increasing success of NAS is attributed to the reliable performance estimation of different architectures. Despite significant progress to date, previous relevant methods suffer from prohibitive computational overheads. To avoid this, we propose an effective yet computationally efficient proxy, namely Trained Batchwise Estimation (TBE), to reliably estimate the performance of different architectures using the early batchwise training statistics. We then integrate TBE into the hardware-aware NAS scenario to search for hardware-efficient architecture solutions. Experimental results clearly show the superiority of TBE over previous relevant state-of-the-art approaches.

关键词： Training Deep learning Neural networks Estimation Computer architecture Reliability

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Work-in-Progress: High-Performance Systolic hardware Accelerator for RBLWE-based Post-Quantum Cryptography

Work-in-Progress: High-Performance Systolic Hardware Acceler...

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ACM/IEEE international conference on hardware/software codesign and system synthesis part of the Embedded systems Week (ESWEEK)

作者： Bao, Tianyou Imana, Jose L. He, Pengzhou Xie, Jiafeng Villanova Univ Dept Elect Comp Engn Villanova PA USA Univ Complutense Dept Comp Architecture Automat Madrid Spain

ISBN: (数字)9781665472944

ISBN: (纸本)9781665472944

Ring-Binary-Learning-with-Errors (RBLWE)-based post-quantum cryptography (PQC) is a promising scheme suitable for lightweight applications. This paper presents an efficient hardware systolic accelerator for RBLWE-based PQC, targeting highperformance applications. We have briefly given the algorithmic background for the proposed design. Then, we have transferred the proposed algorithmic operation into a new systolic accelerator. Lastly, field-programmable gate array (FPGA) implementation results have confirmed the efficiency of the proposed accelerator.

关键词： Polynomial multiplication PQC RBLWE systolic hardware accelerator

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