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2018 ACM/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2018

作者： Zhan, Jinyu Yang, Junhuan Jiang, Wei Li, Yixin School of Information Software Engineering University of Electronic Science Technology of China China

ISBN: (纸本)9781538655627

Non-Volatile Memory (NVM) can be utilized to improve performance of automotive electronic systems, but frequent writings on NVM will decrease its lifetime. In this paper, we propose a Vehicle Dynamic Data Management (VDDM) scheme, which can distinguish the hot or cold data generated by vehicle Electronic Control Units (ECUs) and sensors, and manage the data to reduce the writing operations on NVM of the hybrid main memory. Experimental results show that VDDM can significantly reduce writing operations and prolong lifetime of NVM compared with other approaches. © 2018 IEEE.

关键词： Random access storage

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A simulation framework for domain-specific system-on-chips: work-in-progress 19

A simulation framework for domain-specific system-on-chips: ...

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proceedings of the international conference on hardware/software codesign and system synthesis Companion

作者： Samet E. Arda Anish NK A. Alper Goksoy Joshua Mack Nirmal Kumbhare Anderson L. Sartor Ali Akoglu Radu Marculescu Umit Y. Ogras Arizona State University The University of Arizona Carnegie Mellon University

ISBN: (纸本)9781450369237

Homogeneous general purpose processors provide flexibility to implement a variety of applications and facilitate programmability. In contrast, heterogeneous system-on-chips (SoCs) that combine general purpose and specialized processors offer great potential to achieve higher efficiency while maintaining programming flexibility. In particular, domain-specific SoCs (DSSoC), a class of heterogeneous architectures, tailor the architecture and processing elements (PE) to a specific domain. Hence, they can provide superior energy-efficiency compared to general purpose processors by exploiting the characteristics of target applications.

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A concept of a hardware design environment with the functional language elixir: work-in-progress 19

A concept of a hardware design environment with the function...

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proceedings of the international conference on hardware/software codesign and system synthesis Companion

作者： Hideki Takase Kentaro Matsui Yoshihiro Ueno Masakazu Mori Yuki Hisae Susumu Yamazaki Kyoto University Sakyo-ku Kyoto Japan Delight Systems Co. Ltd. Chuo-ku Fukuoka Japan Karabiner Technology Inc. Chuo-ku Fukuoka Japan The University of Kitakyushu Wakamatsu-ku Kitakushu Japan

ISBN: (纸本)9781450369237

The functional language Elixir is designed to be effective for the application. One of the most considerable feature of Elixir is that it is easy to realize the parallel processing with the standard library, such as Flow. In this paper, we study a design environment for hardware circuits using Elixir as a design language. We propose a synthesize flow for data flow hardware on the FPGA from the native Elixir code. Our method synthesizes functional equivalence circuits from the description of Enum and Flow in Elixir, which are libraries for direct manipulation and parallel processing of data collection in Elixir. Data flow is implemented base on the pipeline operator |> which connects the processing relation of the function by the data processing order. To realize a hardware design environment by Elixir, this paper shares current status of our implementation.

关键词： functional language elixir high-level synthesis

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Synthesizing Secure Reactive Controller for Unmanned Aerial system 6

Synthesizing Secure Reactive Controller for Unmanned Aerial ...

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6th international conference on Dependable systems and Their Applications, DSA 2019

作者： Lu, Wei Shu, Shaoxian Shi, Rao Li, Rui Dong, Wei National University of Defense Technology College of Computer Science Changsha China Hunan Institute of Traffic Engineering Changsha China

ISBN: (纸本)9781728160573

Complex CPS such as VAS got rapid development these years, but also became vulnerable to GPS spoofing, packets injection, buffer-overflow and other malicious attacks. Ensuring the behaviors of VAS always keeping secure no matter how the environment changes, would be a prospective direction for VAS security. This paper aims at presenting a reactive synthesisbased approach to implement the automatic generation of secure VAS controller. First, we study the operating mechanism of VAS and construct a high-Ievel model consisting of actuator and monitor. Besides, we analyze the security threats of VAS from the perspective of hardware, software and data transmission, and then extract the corresponding specifications of security properties with LTL formulas. Based on the VAS model and security specifications, the controller can be constructed by GR(l) synthesis algorithm, which is a two-player game process between VAV and Environment. Finally, we expand the function of LTLMoP platform to construct the automatons for controller in multi-robots system, which provides secure behavior strategies under several typical VAS attack scenarios. © 2020 IEEE.

关键词： Controllers

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FPGA Implementation of Quantized Convolutional Neural Networks 19

FPGA Implementation of Quantized Convolutional Neural Networ...

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19th IEEE international conference on Communication Technology, ICCT 2019

作者： Zhang, Qi Cao, Jian Zhang, Ying Zhang, Shiguang Zhang, Quan Yu, Dunshan School of Software and Microelectronics Peking University China Beijing Aerospace Automatic Control Institute Beijing China

ISBN: (纸本)9781728105352

Convolutional neural networks (CNN) are the most commonly used techniques in computer vision tasks. Image processing methods based on CNN are widely used, especially in areas such as face recognition, target detection, and speech recognition. A large number of CNN computing require the use of dedicated hardware, such as graphics processing units. Since this hardware is not portable in real life, there is an urgent need to apply neural networks to FPGAs. High-level synthesis (HLS) provides a good programming environment for developers, making the programming of FPGA more efficient. In this paper, we will introduce a quantized convolution neural network (QCNN) accelerator architecture based on HLS, which utilizes the parameters that are quantized during training and general processing elements during inference to improve performance. QCNN has fewer parameter operations, so it is advantageous to on-chip storage. The QCNN Accelerator uses a fast algorithm to implement batch normalization, which can greatly reduce hardware consumption while maintaining accuracy. We implemented the proposed architecture on the Nexys Video FPGA platform. The clock frequency is 100 MHz and the peak performance of QCNN reaches 22 GOP/S. Finally, the design and implementation of QCNN accelerator system based on mobile video are introduced. We connect the FPGA with the OV5640 camera to solve the problem of image classification in real-time video transmission. © 2019 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Efficient Decentralized LTL Monitoring Framework Using Tableau Technique

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 87-87页

作者： Bataineh, Omar Rosenblum, David S. Reynolds, Mark Natl Univ Singapore Sch Comp 13 Comp Dr Singapore 117417 Singapore Univ Western Australia Comp Sci & Software Engn 35 Stirling Hwy Crawley WA 6009 Australia

This paper presents a novel framework for decentralized monitoring of Linear Temporal Logic (LTL) formulas, under the situation where processes are synchronous and the formula is represented as a tableau. The tableau technique allows one to construct a semantic tree for the input LTL formula, which can be used to optimize the decentralized monitoring of LTL in various ways. Given a system P and an LTL formula phi, we construct a tableau T-phi. The tableau T-phi is used for two purposes: (a) to synthesize an efficient round-robin communication policy for processes, and (b) to find the minimal ways to decompose the formula and communicate observations of processes in an efficient way. In our framework, processes can propagate truth values of both atomic and compound formulas (non-atomic formulas) depending on the syntactic structure of the input LTL formula and the observation power of processes. We demonstrate that this approach of decentralized monitoring based on tableau construction is more straightforward, more flexible, and more likely to yield efficient solutions than alternative approaches.

关键词： Decentralized monitoring Linear Temporal Logic (LTL) tableau

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Coherent Extension, Composition, and Merging Operators in Contract Models for system Design

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 86-86页

作者： Passerone, Roberto Romeo, Inigo Incer Sangiovanni-Vincentelli, Alberto L. Univ Trento Dipartimento Ingn & Sci Informaz Via Sommar 9 I-38123 Trento Italy Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

Contract models have been proposed to promote and facilitate reuse and distributed development. In this paper, we cast contract models into a coherent formalism used to derive general results about the properties of their operators. We study several extensions of the basic model, including the distinction between weak and strong assumptions and maximality of the specification. We then analyze the disjunction and conjunction operators, and show how they can be broken up into a sequence of simpler operations. This leads to the definition of a new contract viewpoint merging operator, which better captures the design intent in contrast to the more traditional conjunction. The adjoint operation, which we call separation, can be used to repartition the specification into different viewpoints. We show the symmetries of these operations with respect to composition and quotient.

关键词： Interface contract merging conformance separation

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Semantics-Directed Prototyping of hardware Runtime Monitors 29

Semantics-Directed Prototyping of Hardware Runtime Monitors

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29th international Symposium on Rapid system Prototyping, RSP 2018

作者： Harrison, William L. Allwein, Gerard Department of Electrical Engineering Computer Science University of of Missouri ColumbiaMO United States US Naval Research Laboratory WashingtonDC United States

ISBN: (纸本)9781538675571

Building memory protection mechanisms into embedded hardware is attractive because it has the potential to neutralize a host of software-based attacks with relatively small performance overhead. A hardware monitor, being at the lowest level of the system stack, is more difficult to bypass than a software monitor and hardware-based protections are also potentially more fine-grained than is possible in software: an individual instruction executing on a processor may entail multiple memory accesses, all of which may be tracked in hardware. Finally, hardware-based protection can be performed without the necessity of altering application binaries. This article presents a proof-of-concept codesign of a small embedded processor with a hardware monitor protecting against ROP-style code reuse attacks. While the case study is small, it indicates, we argue, an approach to rapid-prototyping runtime monitors in hardware that is quick, flexible, and extensible as well as being amenable to formal verification. © 2018 IEEE.

关键词： High level synthesis

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Enhanced resilient sensor attack detection using fusion interval and measurement history

Enhanced resilient sensor attack detection using fusion inte...

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2018 ACM/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2018

作者： Yang, Kang Wang, Rui Jiang, Yu Luo, Chenxia Guan, Yong Li, Xiaojuan Shi, Zhiping College of Information Engineering Capital Normal University Beijing China School of Software Tsinghua University Beijing China

ISBN: (纸本)9781538655627

For the Cyber-Physical systems which are equipped with multiple sensors that measure the same physical variables, some of the sensors may be subject to malicious attacks and provide the wrong measurements to the controller, resulting in an unsafe state of the system. Although there are several methods for detecting sensor attacks, they may not work well when an attacker manipulates the sensor output very slightly or infrequently over a period of time, e.g., stealth attacks. To address this problem, we take the system dynamics model into account, and propose a novel sensor attack detection algorithm based on historical measurements and fusion intervals. The core idea is to build different fault models for different sensors, add a virtual sensor to use pairwise inconsistencies between two sensors to identify attacks. Finally, we validate the performance of the algorithm on real measurements obtained from the LEGO EV3 ground vehicle, and the results show that the proposed method outperforms state-of-the-art algorithm, especially for stealth attacks, with about 92% promotion in attack detection and identification rate. © 2018 IEEE.

关键词： Cyber Physical system

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Aggressive Energy Reduction for Video Inference with software-only Strategies

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ACM TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 46-46页

作者： Goncalves, Larissa Rozales De Moura, Rafael Fao Carro, Luigi Univ Fed Rio Grande do Sul Porto Alegre RS Brazil

In the past years, several works have proposed custom hardware and software-based techniques for the acceleration of Convolutional Neural Networks (CNNs). Most of these works focus on saving computations by changing the used precision or modifying frame processing. To reach a more aggressive energy reduction, in this paper we propose software-only modifications to the CNNs inference process. Our approach exploits the inherent locality in videos by replacing entire frame computations with a movement prediction algorithm. Furthermore, when a frame must be processed, we avoid energy-demanding floating-point operations, and at the same time reduce memory accesses by employing look-up tables in place of the original convolutions. Using the proposed approach, one can reach significant energy gains of more than 25x for security cameras, and 12x for moving vehicles applications, with only small software modifications.

关键词： Convolutional Neural Networks frame predicton computation reuse

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