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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1554 条记录，以下是241-250 订阅

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Work-in-Progress: A Fast Online Sequential Learning Accelerator for IoT Network Intrusion Detection 12

Work-in-Progress: A Fast Online Sequential Learning Accelera...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Huang, Hantao Khalid, Rai Suleman Liu, Wenye Yu, Hao Nanyang Technol Univ Sch Elect & Elect Engn Singapore Singapore

ISBN: (纸本)9781450351850

Deployment of IoT devices for smart buildings and homes will offer a high level of comfortability with increased energy efficiency;but can also introduce potential cyber-attacks such as network intrusions via linked IoT devices. Due to the low-power and low-latency requirement to secure IoT network, traditional software based security system is not applicable. Instead, an embedded hardware-accelerator based data analytics is more preferred for network intrusion detection. In this paper, we propose an online sequential machine learning hardware accelerator to perform real-time network intrusion detection. A single hidden layer feedforward neural network based learning algorithm is developed with a least-squares solver realized on hardware. Experimental results on a single FPGA achieve a bandwidth of 409.6 Gbps with fast yet low-power network intrusion detection based on a number of benchmarks.

关键词： Intrusion detection hardware Training Field programmable gate arrays Benchmark testing Telecommunication traffic Computer architecture

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RFID Based Motion Direction Estimation in Gate systems

RFID Based Motion Direction Estimation in Gate Systems

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22nd IEEE international conference on Computer Supported Cooperative Work in Design (CSCWD)

作者： Wu Jie Zhu Minghua Xiao Bo He Wei East China Normal Univ MOE Res Ctr Software Hardware Codesign Engn & App Shanghai Peoples R China Minist Publ Secur Antiforgery Dept Inst 3 Shanghai Peoples R China

ISBN: (纸本)9781538614822

The RFD based school gate system is used to estimate students entering or leaving the school when they go through the school gate with RFID tags. In general, the accuracy of the estimation of RFID is sensitive to complex electromagnetic environment changing. For example, the estimation success rate is high in some circumstance but low when there is a car parking in front of directional readers. In this paper, a method is presented by which the direction of the readers would be automatically adjusted according to the received information of the tags. With this method, the accuracy of the estimation of RFID could maintain high even if the electromagnetic environment changes. Experiments also were carried out to evaluate the feasibility of the proposed method. The results showed that the method is highly suitable to keep a stable success rate of motion direction estimation in school gate systems.

关键词： radio frequency identification RSSI gate system motion direction Gaussian distribution

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COMPOSITIONAL ENGINEERING FRAMEWORKS FOR DEVELOPMENT OF SMART CYBER-PHYSICAL systemS: A CRITICAL SURVEY OF THE CURRENT STATE OF PROGRESSION

COMPOSITIONAL ENGINEERING FRAMEWORKS FOR DEVELOPMENT OF SMAR...

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38th American-Society-of-Mechanical-Engineers (ASME) Computers and Information in Engineering (CIE) conference in conjunction with the international Design Engineering Technical Conferes (IDETC)

作者： Horvath, Imre Tepjit, Sirasak Rusak, Zoltan Delft Univ Technol Ind Design Engn Delft Netherlands

ISBN: (纸本)9780791851722

Various system-engineering frameworks (SEFs) have been developed for composable systems, whose overall operation is the sum of the operations of their components. However, smart cyber-physical systems (S-CPSs) are compositional in nature. Their reasoning capability and system knowledge assume an `ampliative' (inter)operation of all hardware, software, or cyberware components. The need for SEFs that support synthesis, modeling, analysis, simulation, verification, and validation of S-CPSs is recognized in the literature. The objective of this paper is a critically review the state of development of compositionality enabling frameworks. Both quantitative and qualitative literature studies were conducted in combination with critical system thinking. The reasoning model used in the qualitative analysis was derived based on the findings of the quantitative analysis. The major observations are: (i) the notion of compositionality is not studied extensively in the context of S-CPSs that do not obey the principle of reductionism, (ii) methodological support of implementation of compositional CPSs seems to be in its infancy, (iii) SEFs may play a crucial role in synthesis, modeling and implementation of S-CPSs, and (iv) SEFs for compositional system design may be realized using the principles of semantic knowledge fusion or meta-synthesis. Our follow up research targets a formal definition and computational implementation of a testable prototype of a specific SEF tool supporting compositional design of reasoning mechanisms.

关键词： Compositionality smart cyber-physical systems system engineering frameworks framework constituents synthesis challenge smart reasoning mechanisms

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Special Session Paper: Exploiting Quality-Energy Tradeoffs with Arbitrary Quantization

Special Session Paper: Exploiting Quality-Energy Tradeoffs w...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Moreau, Thierry Augusto, Felipe Howe, Patrick Alaghi, Armin Ceze, Luis Univ Washington Seattle WA 98195 USA Univ Estadual Campinas Campinas SP Brazil

ISBN: (纸本)9781450351850

Approximate computing aims to expose and exploit quality vs. efficiency tradeoffs to enable ever-more demanding applications on energy-constrained devices such as smartphones, or IoT devices. This paper makes the case for arbitrary quantization as a compelling approximation technique that exposes quality vs. energy tradeoffs and provides practical error guarantees. We present QAPPA (Quality Autotuner for Precision Programmable Accelerators), an autotuning framework for C/C++ programs that automatically minimizes the precision of each arithmetic and memory operation to meet user defined application level quality guarantees. QAPPA integrates energy models of precision scaling mechanisms to produce bandwidth and energy savings estimates for precision scalable accelerator designs. We show that QAPPA can exploit precision scaling mechanisms to meet arbitrary user-provided quality targets on the PERFECT benchmark suite to achieve significant energy savings and memory bandwidth reduction.

关键词： Quantization (signal) Bandwidth Benchmark testing hardware Signal to noise ratio Adders Kernel

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proceedings - 48th Annual IEEE/IFIP international conference on Dependable systems and Networks, DSN 2018

Proceedings - 48th Annual IEEE/IFIP International Conference...

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48th Annual IEEE/IFIP international conference on Dependable systems and Networks, DSN 2018

ISBN: (纸本)9781538655955

The proceedings contain 62 papers. The topics discussed include: a byzantine fault-tolerant ordering service for the hyperledger fabric blockchain platform;Troxy: transparent access to byzantine fault-tolerant systems;SHIRAZ: exploiting system reliability and application resilience characteristics to improve large scale system throughput;understanding and analyzing interconnect errors and network congestion on a large scale HPC system;fast hypervisor recovery without reboot;cost-benefit analysis of moving-target defense in power grids;algorithmic attack synthesis using hybrid dynamics of power grid critical infrastructures;recast: random entanglement for censorship-resistant archival storage;alpha entanglement codes: practical erasure codes to archive data in unreliable environments;IBBE-SGX: cryptographic group access control using trusted execution environments;owl: understanding and detecting concurrency attacks;FAROS: illuminating in-memory injection attacks via provenance-based whole-system dynamic information flow tracking;network-attack-resilient intrusion-tolerant SCADA for the power grid;branching bisimulation and concurrent object verification;efficient transient analysis of a class of compositional fluid stochastic Petri nets;low overhead tag error mitigation for GPU architectures;DAVOS: EDA toolkit for dependability assessment, verification, optimisation and selection of hardware models;a framework for evaluating software on reduced margins hardware;and measuring IPv6 DNS reconnaissance attacks and preventing them using DNS Guard.

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Work-in-Progress: Communication Optimization for Thermal Reliable Many-core systems 12

Work-in-Progress: Communication Optimization for Thermal Rel...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Liu, Weichen Yang, Lei Jiang, Weiwen Guan, Nan Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore Chongqing Univ Coll Comp Sci Chongqing Peoples R China Hong Kong Polytech Univ Dept Comp Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9781450351850

system-level thermal management techniques normally map applications on non-adjacent cores to guarantee the safe temperature in many-core systems, while the communication efficiency will be oppositely affected by long-distance data transmission over conventional Network-on-Chips (NoC). SMART NoC has enabled single-cycle multi-hop bypass channels between distant cores, which can significantly reduce inter-processor communication latency. However, communication efficiency of SMART will be significantly diminished by express bypass break due to communication conflict. In order to achieve communication optimization with guaranteed system thermal reliability, we propose a dynamic re-configuration method for logical interconnection topology through task mapping on top of SMART NoC. Active cores are physically decentralized on chip for better heat dissipation, while communication overhead can be reduced by minimized communication conflict and maximized bypass routing. Applicability and effectiveness of the proposed technique can be improved with significant achievements in reducing communication overhead and improving application performance, compared with state-of-the-art techniques.

关键词： Reliability Silicon Schedules Topology Optimization system-on-chip

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AMVP - a high performance virtual platform using parallel systemC for multicore ARM architectures: work-in-progress 18

AMVP - a high performance virtual platform using parallel sy...

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proceedings of the international conference on hardware/software codesign and system synthesis

作者： Jan Henrik Weinstock Róbert Lajos Bücs Florian Walbroel Rainer Leupers Gerd Ascheid RWTH Aachen University

ISBN: (纸本)9781538655627

This paper presents AMVP - a systemC based simulator for ARM multicore platforms designed as a tool for early SW development during platform bring-up. It uses a parallel systemC simulation approach to counter the performance slowdown incurred when simulating multi-processor designs. AMVP is sufficiently detailed to support running and debugging unmodified SW images of popular benchmark applications and modern OS kernels like Linux.

关键词： parallel systemC simulation parallel discrete event simulation electronic system level

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A chip-level security framework for assessing sensor data integrity: work-in-progress 18

A chip-level security framework for assessing sensor data in...

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proceedings of the international conference on hardware/software codesign and system synthesis

作者： Taimour Wehbe Vincent J. Mooney David C. Keezer Georgia Institute of Technology

ISBN: (纸本)9781538655627

The continuously increasing inter-connectivity of sensor nodes that form the basis of the Internet-of-Things results in new avenues of attack exploitable by adversaries to maliciously modify data captured by these nodes. In this work, we present a framework for detecting malicious hardware alterations that attempt to attack state-of-the-art microchips that form these sensor nodes. Specifically, we focus on extremely small hardware Trojans (HTs) that attempt to modify sensor data right away as the data is received on a state-of-the-art chip fabricated in an untrusted facility. We present a dual-chip approach composed of an untrusted state-of-the-art prover chip and a trusted verifier chip, where the verifier continuously challenges the prover at run-time to ensure correct operation and assess the integrity of the captured data. Our preliminary analysis of the proposed mechanism shows that HT attacks anywhere on the untrusted state-of-the-art chip are detected and flagged preventing maliciously altered data to be transmitted out of the sensor node.

关键词： embedded systems security hardware trojans malicious design modifications sensor networks data integrity security in hardware hardware attacks and countermeasures

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On leveraging approximations for exact system-level design space exploration: work-in-progress 18

On leveraging approximations for exact system-level design s...

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proceedings of the international conference on hardware/software codesign and system synthesis

作者： Kai Neubauer Christian Haubelt Philipp Wanko Torsten Schaub University of Rostock Germany University of Potsdam Germany

ISBN: (纸本)9781538655627

In order to find good design points for embedded systems, an efficient exploration of the design space is imperative. The ever-increasing complexity of embedded systems, however, results in a deterioration of the overall exploration performance. The DSE essentially consists of two parts: (1) the search for feasible solutions and (2) the evaluation of found feasible solutions. While the search has been massively improved by ASPmT-based strategies, the evaluation emerges as the main bottleneck. Tragically, evaluating bad solutions takes as much time as evaluating good ones. Hence, in this paper we study the utilization of approximations in the evaluation process integrated in an ASPmT-based DSE to identify bad solutions more quickly while still retaining the exact Pareto-front.

关键词： system-level design approximation design space exploration

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Advancing remote attestation via computer-aided formal verification of designs and synthesis of executables: opinion 19

Advancing remote attestation via computer-aided formal verif...

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proceedings of the 12th conference on Security and Privacy in Wireless and Mobile Networks

作者： Karim Eldefrawy Gene Tsudik SRI International UC Irvine

ISBN: (纸本)9781450367264

Remote Attestation (RA) of embedded/smart/IoT devices is a very important issue on today's security landscape. RA enables a verifier to measures the current internal memory state of an untrusted remote device (prover). RA helps the verifier establish a static or dynamic root of trust in prover. Despite much prior work, state-of-the-art RA techniques unfortunately still lack any solid foundation and offer no ironclad security, safety or robustness guarantees. This paper argues that computer-aided formal verification, and synthesis of executables, of RA protocols and hybrid (software-hardware) architectures is required and currently unaddressed. We believe that this is achievable with current (computer-aided) formal methods frameworks and tools, and that this can help advance and mature RA research if used to establish more rigorous and clear security arguments. To support our opinion, we highlight several examples where subtle issues were missed in the design and security analysis of RA techniques. Despite deceptive simplicity of such protocols, manual analyses and ad hoc implementations often lead to over-simplification of (and subsequent glossing over) important details in the underlying processor and system architectures. Computer-aided formal verification forces a more scrupulous and disciplined consideration of such details, since, otherwise, verification simply fails. The key objective of the research direction we propose is to increase confidence in correctness and security guarantees of current and future RA techniques and their implementations.

关键词： secure remote attestation formal verification formal methods

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